RuigeLee
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ca60205abc
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反转FSMC信号电平，尝试测试
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2024-03-06 17:41:28 +08:00 |
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RuigeLee
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dba35faa6e
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主机模拟FSMC模式不能背靠背传送，否则会出CRC以及CDR
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2024-02-22 16:34:01 +08:00 |
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RuigeLee
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411ad21db6
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新lvds代码仿真目前不影响原功能
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2024-01-26 17:34:22 +08:00 |
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RuigeLee
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d729dfbe7e
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FSMC跑测试
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2024-01-09 17:48:23 +08:00 |
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RuigeLee
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d74a4754a7
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FSMC重构，使用100MHZ过采样
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2024-01-08 18:01:29 +08:00 |
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RuigeLee
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2f09a7245f
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Revert "stage"
This reverts commit 98b13e6b94.
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2023-12-27 17:44:50 +08:00 |
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RuigeLee
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98b13e6b94
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stage
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2023-12-27 17:44:42 +08:00 |
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RuigeLee
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afd21f6913
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临时调试修改，需要revert
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2023-12-26 14:40:59 +08:00 |
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RuigeLee
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b098ca963e
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test pass
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2023-09-14 19:16:17 +08:00 |
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RuigeLee
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6fd836fc9c
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new version
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2023-09-12 17:51:32 +08:00 |
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RuigeLee
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527f6bd761
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fix sync misunderstanding
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2023-09-11 17:39:19 +08:00 |
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RuigeLee
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05a905ac39
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merge mirror read/write
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2023-09-08 18:47:13 +08:00 |
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RuigeLee
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bf835014bc
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16bit fsmc data; 16*2 reg, 100us
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2023-09-08 16:37:31 +08:00 |
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RuigeLee
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145db92202
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test pass
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2023-08-31 17:39:12 +08:00 |
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RuigeLee
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d226487a5e
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BUG FIX
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2023-08-31 15:10:18 +08:00 |
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RuigeLee
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860e24ca99
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check mst
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2023-08-30 17:32:19 +08:00 |
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RuigeLee
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c0645cfe16
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update sram; bug fixed; lvds failed
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2023-08-23 19:32:41 +08:00 |
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Ruige Lee (WSL)
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37ac7817d7
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fix sram
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2023-08-21 14:52:21 +08:00 |
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RuigeLee
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5f15e94ae3
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bug override
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2023-08-21 11:51:59 +08:00 |
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RuigeLee
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31a822091b
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Revert "devide gowin file"
This reverts commit d162b8f75c.
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2023-08-21 11:51:25 +08:00 |
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RuigeLee
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d162b8f75c
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devide gowin file
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2023-08-21 11:46:50 +08:00 |
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RuigeLee
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589fc528a0
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compile pass
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2023-08-20 15:50:11 +08:00 |
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Ruige Lee
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f3a44f0b31
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slv
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2023-08-18 12:10:47 +00:00 |
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RuigeLee
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6fa2ef5f6e
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porta
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2023-08-16 22:25:30 +08:00 |
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Ruige Lee
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bbd0f0b887
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sync
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2023-08-16 06:12:49 +00:00 |
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Ruige Lee
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6c2f0b02f8
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FSMC
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2023-08-15 08:42:56 +00:00 |
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Ruige Lee
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939fa22be5
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wrapper of mst and slv
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2023-08-15 02:59:10 +00:00 |
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RuigeLee
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3211e21e11
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wrapper
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2023-08-14 22:46:50 +08:00 |
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RuigeLee
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1c7a226a70
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add function demo
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2023-08-09 14:43:24 +08:00 |
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RuigeLee
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68e0a6a055
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test pass
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2023-08-07 11:40:14 +08:00 |
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RuigeLee
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a041c7732a
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over sample in spi
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2023-08-07 10:15:56 +08:00 |
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RuigeLee
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d09aff40f2
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timing close
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2023-08-02 15:17:16 +08:00 |
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RuigeLee
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5d43600680
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fpga sync
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2023-08-01 15:50:53 +08:00 |
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RuigeLee
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35e6fcdb52
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mst test pass
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2023-08-01 14:44:05 +08:00 |
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RuigeLee
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24800cce9d
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spi compile pass
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2023-07-31 22:56:09 +08:00 |
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RuigeLee
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3aa4ca17d4
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all test pass
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2023-07-28 20:42:35 +08:00 |
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RuigeLee
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2048a4d286
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first test
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2023-07-28 15:38:46 +08:00 |
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Ruige
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85fe9175e6
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backplaneslv compile pass
Signed-off-by: Ruige <295054118@whut.edu.cn>
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2023-07-25 21:05:43 +08:00 |
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RuigeLee
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b1fd2db2e0
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backboard
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2023-07-24 19:31:32 +08:00 |
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