RuigeLee
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3b6b3bc14b
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增加跨时钟域，准备切换分支
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2023-10-08 10:12:49 +08:00 |
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RuigeLee
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2435f7fa01
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rx初步优化 编译通过
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2023-10-07 16:44:13 +08:00 |
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RuigeLee
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fd0f1347cf
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半成品，剥离tilelinkTx，在mtx不会远大于clock；tx_FIFO不会极限小的情况下，无跨时钟保护是允许的
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2023-09-28 18:45:14 +08:00 |
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RuigeLee
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f3a35964f8
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opt: tx/rx传输必须32比特对齐，不再支持非对齐操作
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2023-09-27 16:31:56 +08:00 |
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RuigeLee
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61f15c9ebe
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bug:rx 大小端总线传输非对齐模式下mask错误
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2023-09-27 16:14:04 +08:00 |
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RuigeLee
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e6f34762e8
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状态机化简
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2023-09-26 21:41:19 +08:00 |
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RuigeLee
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25a5c81668
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bug: 异步复位信号缺失
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2023-09-26 21:40:47 +08:00 |
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RuigeLee
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51c39369c8
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要求所有tx/rx时钟域异步复位
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2023-09-25 14:18:27 +08:00 |
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RuigeLee
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5ff118f527
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rx: big-endian to little-endian
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2023-09-21 16:55:22 +08:00 |
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RuigeLee
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e42c6a3b11
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dma cache to sys-port
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2023-09-20 11:17:30 +08:00 |
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RuigeLee
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8a9aa0436c
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a sign for tx/rx clock merge
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2023-09-19 18:03:30 +08:00 |
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RuigeLee
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4702991e69
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tx: big-endian to little-endian
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2023-09-19 17:54:36 +08:00 |
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RuigeLee
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440cefb02a
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we use async reset for different clock now
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2023-07-24 19:31:20 +08:00 |
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RuigeLee
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21f8547273
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ethreg Test pass
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2023-07-21 16:38:02 +08:00 |
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RuigeLee
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0b48e2cd2b
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compile pass
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2023-07-20 14:58:59 +08:00 |
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RuigeLee
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fa748b7de9
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Revert "create register node"
This reverts commit e558356a22.
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2023-07-20 10:35:56 +08:00 |
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RuigeLee
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e558356a22
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create register node
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2023-07-20 10:01:59 +08:00 |
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RuigeLee
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e3e1f6b6cb
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a new top for fpga; port mac-master to mem
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2023-07-17 21:41:34 +08:00 |
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RuigeLee
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25584bf6f5
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successfully interger in rocketchip
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2023-07-13 17:38:01 +08:00 |
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RuigeLee
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63be80135c
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tl to axi in single device
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2023-07-12 17:24:42 +08:00 |
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RuigeLee
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242765f106
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add trait
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2023-07-11 23:05:44 +08:00 |
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RuigeLee
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8b2121959e
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中断节点化
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2023-07-11 22:02:41 +08:00 |
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RuigeLee
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2d720b7c8d
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remove istilelink parameter
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2023-07-11 17:45:32 +08:00 |
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RuigeLee
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44048ea7d9
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remove all wishbone
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2023-07-11 17:38:18 +08:00 |
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RuigeLee
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3037d31028
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move tlsram to chisel
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2023-07-11 00:00:26 +08:00 |
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RuigeLee
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67f93bb464
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强拆wbmst，删除了burst特性，待功能测试通过后重做
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2023-07-07 21:43:06 +08:00 |
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RuigeLee
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9322f63bc5
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跨时钟域有严重设计缺陷
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2023-07-06 22:11:49 +08:00 |
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RuigeLee
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78a2f4ba47
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ready to test tilelink slv
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2023-07-04 23:36:34 +08:00 |
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RuigeLee
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5bd8b261bf
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compile tilelink
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2023-07-04 17:37:41 +08:00 |
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RuigeLee
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01853cecd1
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parameter, switch of diff slv bus
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2023-07-04 15:40:51 +08:00 |
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RuigeLee
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6efd11322b
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io merge
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2023-07-04 14:26:24 +08:00 |
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RuigeLee
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3886583b2a
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bug fixed
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2023-07-04 13:07:33 +08:00 |
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RuigeLee
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fd9bebe897
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compile and realign pass
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2023-07-04 10:00:08 +08:00 |
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RuigeLee
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0303ca21fb
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top layer and some bugs fixed
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2023-07-03 23:51:01 +08:00 |
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RuigeLee
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38bcf0dcf0
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tilelink should not add here
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2023-07-03 16:25:41 +08:00 |
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RuigeLee
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c65edfe4ae
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merge wb into tilelink files
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2023-06-30 20:21:03 +08:00 |
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RuigeLee
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374c6ecde0
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this is the last equal commit
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2023-06-30 16:14:58 +08:00 |
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RuigeLee
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d4ed6f39a0
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opt
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2023-06-30 16:00:02 +08:00 |
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RuigeLee
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546fea5903
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opt
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2023-06-30 14:46:23 +08:00 |
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RuigeLee
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cecf3caddc
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opt
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2023-06-29 23:28:05 +08:00 |
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RuigeLee
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59a2f2e054
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opt
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2023-06-29 21:14:51 +08:00 |
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RuigeLee
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61e36c59d8
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wishbone test pass
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2023-06-29 18:29:54 +08:00 |
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RuigeLee
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7aee6496f9
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wishbone almost
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2023-06-28 23:43:03 +08:00 |
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RuigeLee
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9e3786785c
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macregister
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2023-06-26 21:55:20 +08:00 |
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RuigeLee
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0fc0325969
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pass tx rx status ctrl
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2023-06-25 22:53:44 +08:00 |
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RuigeLee
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614958408d
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MacTx
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2023-06-24 19:29:49 +08:00 |
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RuigeLee
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505aa7326a
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finish macrx
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2023-06-21 21:55:16 +08:00 |
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RuigeLee
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ac7db49089
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compare test pass
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2023-06-20 18:26:59 +08:00 |
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1bc7d68af8
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MIIM write out
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2023-06-18 13:06:31 +00:00 |
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f431b875f1
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create files
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2023-06-18 08:34:44 +00:00 |
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