28 Commits

Author	SHA1	Message	Date
RuigeLee	31213302aa	尝试流片顶层	2023-11-14 17:03:19 +08:00
RuigeLee	629d9486d1	完成编译，准备接入CPU查看信号逻辑	2023-10-17 16:38:18 +08:00
RuigeLee	51c39369c8	要求所有tx/rx时钟域异步复位	2023-09-25 14:18:27 +08:00
RuigeLee	589fc528a0	compile pass	2023-08-20 15:50:11 +08:00
RuigeLee	50403930a9	check chain	2023-08-09 16:34:29 +08:00
RuigeLee	68e0a6a055	test pass	2023-08-07 11:40:14 +08:00
RuigeLee	a041c7732a	over sample in spi	2023-08-07 10:15:56 +08:00
RuigeLee	d09aff40f2	timing close	2023-08-02 15:17:16 +08:00
RuigeLee	5d43600680	fpga sync	2023-08-01 15:50:53 +08:00
RuigeLee	35e6fcdb52	mst test pass	2023-08-01 14:44:05 +08:00
RuigeLee	24800cce9d	spi compile pass	2023-07-31 22:56:09 +08:00
RuigeLee	2048a4d286	first test	2023-07-28 15:38:46 +08:00
Ruige	85fe9175e6	backplaneslv compile pass ... Signed-off-by: Ruige <295054118@whut.edu.cn>	2023-07-25 21:05:43 +08:00
RuigeLee	21f8547273	ethreg Test pass	2023-07-21 16:38:02 +08:00
RuigeLee	0b48e2cd2b	compile pass	2023-07-20 14:58:59 +08:00
RuigeLee	02ec89bda5	axi opt	2023-07-12 18:43:28 +08:00
RuigeLee	63be80135c	tl to axi in single device	2023-07-12 17:24:42 +08:00
RuigeLee	8b2121959e	中断节点化	2023-07-11 22:02:41 +08:00
RuigeLee	2d720b7c8d	remove istilelink parameter	2023-07-11 17:45:32 +08:00
RuigeLee	44048ea7d9	remove all wishbone	2023-07-11 17:38:18 +08:00
RuigeLee	3037d31028	move tlsram to chisel	2023-07-11 00:00:26 +08:00
RuigeLee	0303ca21fb	top layer and some bugs fixed	2023-07-03 23:51:01 +08:00
RuigeLee	61e36c59d8	wishbone test pass	2023-06-29 18:29:54 +08:00
RuigeLee	9e3786785c	macregister	2023-06-26 21:55:20 +08:00
RuigeLee	0fc0325969	pass tx rx status ctrl	2023-06-25 22:53:44 +08:00
RuigeLee	505aa7326a	finish macrx	2023-06-21 21:55:16 +08:00
RuigeLee	ac7db49089	compare test pass	2023-06-20 18:26:59 +08:00
Ruige Lee	e84986160f	Initial commit	2023-06-18 12:41:33 +08:00