RuigeLee
|
3e4964852e
|
人机交互界面完成
|
2023-10-24 17:42:25 +08:00 |
|
RuigeLee
|
e99ff4789f
|
tx 首尾修正
|
2023-10-24 16:27:30 +08:00 |
|
RuigeLee
|
701ba16491
|
cleanup
|
2023-10-24 15:34:30 +08:00 |
|
RuigeLee
|
86fb086bd2
|
tx 32转8 基本测试通过
|
2023-10-24 14:00:51 +08:00 |
|
RuigeLee
|
54991d8cb5
|
Tx尝试统一接口，失败
|
2023-10-23 23:36:01 +08:00 |
|
RuigeLee
|
faa46be8ef
|
Rx的req resp跨时钟架构
|
2023-10-23 22:58:36 +08:00 |
|
RuigeLee
|
bf66bae475
|
rx 通道基本完成32转8，存在跨时钟域风险
|
2023-10-21 21:08:40 +08:00 |
|
RuigeLee
|
69ccc32603
|
在32数据通道下传输正确
|
2023-10-20 20:56:44 +08:00 |
|
RuigeLee
|
f17d405369
|
Rx DMA 传输正确
|
2023-10-20 15:49:24 +08:00 |
|
RuigeLee
|
0215add0d4
|
rx DMA编译完成
|
2023-10-20 14:42:15 +08:00 |
|
RuigeLee
|
c5f9b4d74f
|
未完成，尝试建立DMA
|
2023-10-19 18:31:26 +08:00 |
|
RuigeLee
|
70922ecb44
|
拓扑修改，编译通过
|
2023-10-19 15:24:26 +08:00 |
|
RuigeLee
|
d77c69aa5a
|
接收数据流解耦初步测试成功
|
2023-10-18 17:11:56 +08:00 |
|
RuigeLee
|
629d9486d1
|
完成编译，准备接入CPU查看信号逻辑
|
2023-10-17 16:38:18 +08:00 |
|
RuigeLee
|
7c71c005f8
|
基本清理完成
|
2023-10-14 12:36:37 +08:00 |
|
RuigeLee
|
0c60fbfb15
|
未完成清理tx，txready初始化为true
|
2023-10-13 18:18:02 +08:00 |
|
RuigeLee
|
ceef60b95c
|
断言不会发生tx Underrun
|
2023-10-13 15:21:53 +08:00 |
|
RuigeLee
|
bb35dffb84
|
未完成tx拆解
|
2023-10-12 18:37:12 +08:00 |
|
RuigeLee
|
af4e95fa47
|
增加rx功能buff，底座
|
2023-10-12 17:04:10 +08:00 |
|
RuigeLee
|
38550d723b
|
rx数据通道已经拆解
|
2023-10-12 15:42:49 +08:00 |
|
RuigeLee
|
774c00a97c
|
未完成，重构rx tilelink，使能仅依赖于pingpong是否准备好
|
2023-10-11 18:48:05 +08:00 |
|
RuigeLee
|
82a6805e05
|
异步fifo
|
2023-10-10 16:48:32 +08:00 |
|
RuigeLee
|
201ab2579b
|
化简代码
|
2023-10-08 18:27:49 +08:00 |
|
RuigeLee
|
31d2d86f01
|
bug:阶跃错误
|
2023-10-08 15:54:40 +08:00 |
|
RuigeLee
|
aec4160431
|
代码清理
|
2023-10-08 15:37:54 +08:00 |
|
RuigeLee
|
a331599ad4
|
bug: 信号同步时钟域错误
|
2023-10-08 15:30:08 +08:00 |
|
RuigeLee
|
92a6f6b5c3
|
move out rx
|
2023-10-08 15:13:35 +08:00 |
|
RuigeLee
|
115f216139
|
moveout tx
|
2023-10-08 11:34:36 +08:00 |
|
RuigeLee
|
3b6b3bc14b
|
增加跨时钟域，准备切换分支
|
2023-10-08 10:12:49 +08:00 |
|
RuigeLee
|
2435f7fa01
|
rx初步优化 编译通过
|
2023-10-07 16:44:13 +08:00 |
|
RuigeLee
|
fd0f1347cf
|
半成品，剥离tilelinkTx，在mtx不会远大于clock；tx_FIFO不会极限小的情况下，无跨时钟保护是允许的
|
2023-09-28 18:45:14 +08:00 |
|
RuigeLee
|
f3a35964f8
|
opt: tx/rx传输必须32比特对齐，不再支持非对齐操作
|
2023-09-27 16:31:56 +08:00 |
|
RuigeLee
|
61f15c9ebe
|
bug:rx 大小端总线传输非对齐模式下mask错误
|
2023-09-27 16:14:04 +08:00 |
|
RuigeLee
|
e6f34762e8
|
状态机化简
|
2023-09-26 21:41:19 +08:00 |
|
RuigeLee
|
25a5c81668
|
bug: 异步复位信号缺失
|
2023-09-26 21:40:47 +08:00 |
|
RuigeLee
|
51c39369c8
|
要求所有tx/rx时钟域异步复位
|
2023-09-25 14:18:27 +08:00 |
|
RuigeLee
|
5ff118f527
|
rx: big-endian to little-endian
|
2023-09-21 16:55:22 +08:00 |
|
RuigeLee
|
e42c6a3b11
|
dma cache to sys-port
|
2023-09-20 11:17:30 +08:00 |
|
RuigeLee
|
8a9aa0436c
|
a sign for tx/rx clock merge
|
2023-09-19 18:03:30 +08:00 |
|
RuigeLee
|
4702991e69
|
tx: big-endian to little-endian
|
2023-09-19 17:54:36 +08:00 |
|
RuigeLee
|
40b558d3a2
|
sync
|
2023-09-15 15:36:44 +08:00 |
|
RuigeLee
|
b098ca963e
|
test pass
|
2023-09-14 19:16:17 +08:00 |
|
RuigeLee
|
6fd836fc9c
|
new version
|
2023-09-12 17:51:32 +08:00 |
|
RuigeLee
|
527f6bd761
|
fix sync misunderstanding
|
2023-09-11 17:39:19 +08:00 |
|
RuigeLee
|
05a905ac39
|
merge mirror read/write
|
2023-09-08 18:47:13 +08:00 |
|
RuigeLee
|
bf835014bc
|
16bit fsmc data; 16*2 reg, 100us
|
2023-09-08 16:37:31 +08:00 |
|
RuigeLee
|
145db92202
|
test pass
|
2023-08-31 17:39:12 +08:00 |
|
RuigeLee
|
d226487a5e
|
BUG FIX
|
2023-08-31 15:10:18 +08:00 |
|
RuigeLee
|
860e24ca99
|
check mst
|
2023-08-30 17:32:19 +08:00 |
|
RuigeLee
|
c0645cfe16
|
update sram; bug fixed; lvds failed
|
2023-08-23 19:32:41 +08:00 |
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