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bug: 16相位补充相 欠了一相

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Ruige Lee
2025-08-14 19:20:49 +08:00
parent 035109bee1
commit fc917054ed
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -79,7 +79,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) } sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
} }
for( i <- 16 until 23 ){ for( i <- 16 until 23 ){
sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))} sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))}
} }