From fc917054ed49fa3132309c4e01423207efe1fda8 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Thu, 14 Aug 2025 19:20:49 +0800
Subject: [PATCH] =?UTF-8?q?bug:=2016=E7=9B=B8=E4=BD=8D=E8=A1=A5=E5=85=85?=
 =?UTF-8?q?=E7=9B=B8=20=E6=AC=A0=E4=BA=86=E4=B8=80=E7=9B=B8?=
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---
 src/main/scala/backBoard/ebus/CDRIn.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 6290a81..991b743 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -79,7 +79,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
   for( i <- 16 until 23 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
+    sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))}
   }