diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 6290a81..991b743 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -79,7 +79,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
   for( i <- 16 until 23 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
+    sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))}
   }