bug: 16相位补充相欠了一相

2025-08-14 19:20:49 +08:00
parent 035109bee1
commit fc917054ed
1 changed files with 1 additions and 1 deletions
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -79,7 +79,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
    sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
  }
  for( i <- 16 until 23 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
+    sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))}
  }