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do的下行寄存器没有改到

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RuigeLee
2024-09-05 15:17:20 +08:00
parent 838729a694
commit f7697eed6b
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/backBoard/Dout16.scala
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@@ -31,11 +31,11 @@ with BackBoardSlvOut16{
LED_ERR := v24Det LED_ERR := v24Det
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
outReg := Cat(downRegTemp(3), downRegTemp(2)) outReg := Cat(downRegTemp(13), downRegTemp(12))
} }
when( isCrcPass & downRegTemp(0)(3,0) === 1.U & downRegTemp(2).extract(0) ){ when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
mthodReg := Cat(downRegTemp(3), downRegTemp(2)) mthodReg := Cat(downRegTemp(9), downRegTemp(8))
valueReg := Cat(downRegTemp(5), downRegTemp(4)) valueReg := Cat(downRegTemp(11), downRegTemp(10))
} }
outRegSync := RegEnable( outReg, 0.U, isUpdate ) outRegSync := RegEnable( outReg, 0.U, isUpdate )