From f7697eed6b6330bf3379e2c9b229836e5659b25b Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 5 Sep 2024 15:17:20 +0800 Subject: [PATCH] =?UTF-8?q?do=E7=9A=84=E4=B8=8B=E8=A1=8C=E5=AF=84=E5=AD=98?= =?UTF-8?q?=E5=99=A8=E6=B2=A1=E6=9C=89=E6=94=B9=E5=88=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/Dout16.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/Dout16.scala b/src/main/scala/backBoard/Dout16.scala index 3ba70af..23e8983 100644 --- a/src/main/scala/backBoard/Dout16.scala +++ b/src/main/scala/backBoard/Dout16.scala @@ -31,11 +31,11 @@ with BackBoardSlvOut16{ LED_ERR := v24Det when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ - outReg := Cat(downRegTemp(3), downRegTemp(2)) + outReg := Cat(downRegTemp(13), downRegTemp(12)) } - when( isCrcPass & downRegTemp(0)(3,0) === 1.U & downRegTemp(2).extract(0) ){ - mthodReg := Cat(downRegTemp(3), downRegTemp(2)) - valueReg := Cat(downRegTemp(5), downRegTemp(4)) + when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ + mthodReg := Cat(downRegTemp(9), downRegTemp(8)) + valueReg := Cat(downRegTemp(11), downRegTemp(10)) } outRegSync := RegEnable( outReg, 0.U, isUpdate )