硬件错误中断捕捉边缘
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@@ -1165,12 +1165,17 @@ trait InterfaceSystem{ this: InterfaceBase =>
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intStatus(19) := true.B
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}
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val intHWErr = Seq(
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( ~RegNext(io.intHWTrig(0), false.B) & io.intHWTrig(0)),
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( ~RegNext(io.intHWTrig(1), false.B) & io.intHWTrig(1))
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)
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//下行接收硬件错误
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when( io.intHWTrig(0) ){
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when( intHWErr(0) ){
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intStatus(29) := true.B
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}
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//上行接收硬件错误
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when( io.intHWTrig(1) ){
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when( intHWErr(1) ){
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intStatus(30) := true.B
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}
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@@ -1206,8 +1211,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
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(0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
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(0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
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isMstRecCRCErr | //override //主站状态下19为上行crc接收错误 //不会同时发生
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io.intHWTrig(0) | //下行接收硬件错误
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io.intHWTrig(1) //上行接收硬件错误
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intHWErr(0) | //下行接收硬件错误
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intHWErr(1) //上行接收硬件错误
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when( intPulseResetCnt === intPulseWidth ){
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intPulse := false.B
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