From f5336f1dc511074cf9caa136909724de260fc892 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 28 Aug 2025 10:28:59 +0800 Subject: [PATCH] =?UTF-8?q?=E7=A1=AC=E4=BB=B6=E9=94=99=E8=AF=AF=E4=B8=AD?= =?UTF-8?q?=E6=96=AD=E6=8D=95=E6=8D=89=E8=BE=B9=E7=BC=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 0270c66..812397f 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -1165,12 +1165,17 @@ trait InterfaceSystem{ this: InterfaceBase => intStatus(19) := true.B } + + val intHWErr = Seq( + ( ~RegNext(io.intHWTrig(0), false.B) & io.intHWTrig(0)), + ( ~RegNext(io.intHWTrig(1), false.B) & io.intHWTrig(1)) + ) //下行接收硬件错误 - when( io.intHWTrig(0) ){ + when( intHWErr(0) ){ intStatus(29) := true.B } //上行接收硬件错误 - when( io.intHWTrig(1) ){ + when( intHWErr(1) ){ intStatus(30) := true.B } @@ -1206,8 +1211,8 @@ trait InterfaceSystem{ this: InterfaceBase => (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求 (0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19 isMstRecCRCErr | //override //主站状态下19为上行crc接收错误 //不会同时发生 - io.intHWTrig(0) | //下行接收硬件错误 - io.intHWTrig(1) //上行接收硬件错误 + intHWErr(0) | //下行接收硬件错误 + intHWErr(1) //上行接收硬件错误 when( intPulseResetCnt === intPulseWidth ){ intPulse := false.B