diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 0270c66..812397f 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -1165,12 +1165,17 @@ trait InterfaceSystem{ this: InterfaceBase =>
     intStatus(19) := true.B
   }
 
+
+  val intHWErr = Seq(
+   ( ~RegNext(io.intHWTrig(0), false.B) & io.intHWTrig(0)),
+   ( ~RegNext(io.intHWTrig(1), false.B) & io.intHWTrig(1))
+  )
   //下行接收硬件错误
-  when( io.intHWTrig(0) ){
+  when( intHWErr(0) ){
     intStatus(29) := true.B
   }
   //上行接收硬件错误
-  when( io.intHWTrig(1) ){
+  when( intHWErr(1) ){
     intStatus(30) := true.B
   }
 
@@ -1206,8 +1211,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
     (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
     (0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
     isMstRecCRCErr | //override //主站状态下19为上行crc接收错误 //不会同时发生
-    io.intHWTrig(0) | //下行接收硬件错误
-    io.intHWTrig(1)   //上行接收硬件错误
+    intHWErr(0) | //下行接收硬件错误
+    intHWErr(1)   //上行接收硬件错误
 
   when( intPulseResetCnt === intPulseWidth ){
     intPulse := false.B