弃用高频率采样CDR的例化
Merge branch 'mp_eb_dev_多采样全表决' into mp_eb_dev * mp_eb_dev_多采样全表决: 调整解锁条件为10个连续0 增加一个锁定可以暂时解决发送失败问题 滤波 表决 鉴相同时存在 enhance 要求先跨时钟，再进行后续表决 Revert "16相位改8相位" 16相位改8相位 bug: 16相位补充相 欠了一相 Revert "改6相位，从一个pll出，测试" Revert "尝试3相位" 尝试3相位 改6相位，从一个pll出，测试 拉出测试IO Revert "4多相位效果明显更好" 4多相位效果明显更好 16相位操作还是卡 # Conflicts: # src/main/scala/backBoard/ebus/CDRIn.scala
This commit is contained in:
Ruige Lee
@@ -70,90 +70,82 @@ trait CDRInMultiSample{ this: CDRInBase =>
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//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
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val multiCLK = IO(Input(Vec(16, Bool())))
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val multiCLK = IO(Input(Vec(clkNum, Bool())))
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// val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
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val sampleReg = for( i <- 0 until 16 ) yield {
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withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
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val sampleReg = Wire(Vec(clkNum, Bool()))
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for( i <- 0 until clkNum ) {
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sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
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}
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val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
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for( i <- 0 until clkNum ){
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sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
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}
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for( i <- clkNum until 2*clkNum ){
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sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1)
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}
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/*
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val flitReg =
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for( i <- 1 until 22 ) yield {
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(sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
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(sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
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(sampleReg_sync(i+0) & sampleReg_sync(i+1))
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}
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val asyncSerDat = PopCount(flitReg) >= 11.U
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*/
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val flitReg =
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if(false){
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for( i <- 0 until 16 ) yield {
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sampleReg(i)
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for( i <- 1 until (2*clkNum)-1 ) yield {
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(sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
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(sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
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(sampleReg_sync(i+0) & sampleReg_sync(i+1))
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}
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} else if (false){ //5选3 多数投票 滤波
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for( i <- 0 until 16 ) yield {
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withClockAndReset(multiCLK((i+3)%16).asClock, reset.asBool){ RegNext(
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(sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
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(sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
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(sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+2)%16)) |
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(sampleReg((i-2+16)%16) & sampleReg((i+0)%16) & sampleReg((i+1)%16)) |
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(sampleReg((i-2+16)%16) & sampleReg((i+0)%16) & sampleReg((i+2)%16)) |
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(sampleReg((i-2+16)%16) & sampleReg((i+1)%16) & sampleReg((i+2)%16)) |
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(sampleReg((i-1+16)%16) & sampleReg((i+0)%16) & sampleReg((i+1)%16)) |
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(sampleReg((i-1+16)%16) & sampleReg((i+0)%16) & sampleReg((i+2)%16)) |
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(sampleReg((i-1+16)%16) & sampleReg((i+1)%16) & sampleReg((i+2)%16)) |
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(sampleReg((i-0)%16) & sampleReg((i+1)%16) & sampleReg((i+2)%16))
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)}
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}
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} else { //3选2 多数投票 滤波
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for( i <- 0 until 16 ) yield {
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withClockAndReset(multiCLK((i+2)%16).asClock, reset.asBool){ RegNext(
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(sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
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(sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
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(sampleReg((i+0)%16) & sampleReg((i+1)%16))
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)}
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val clearCnt = Reg(UInt(4.W))
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val arbLock = Reg(UInt( clkNum.W ))
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val isLock = RegInit(false.B)
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when( sampleReg.reduce(_|_) === false.B ){
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when( clearCnt =/= 10.U ){
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clearCnt := clearCnt + 1.U
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}
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} .otherwise{
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clearCnt := 0.U
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}
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val arbLock = Reg(UInt( 16.W ))
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//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
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when( flitReg(0) ^ flitReg(1) ){
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arbLock := "b1".U(16.W) << 2
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} .elsewhen( flitReg(1) ^ flitReg(2) ){
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arbLock := "b1".U(16.W) << 3
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} .elsewhen( flitReg(2) ^ flitReg(3) ){
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arbLock := "b1".U(16.W) << 4
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} .elsewhen( flitReg(3) ^ flitReg(4) ){
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arbLock := "b1".U(16.W) << 5
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} .elsewhen( flitReg(4) ^ flitReg(5) ){
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arbLock := "b1".U(16.W) << 6
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} .elsewhen( flitReg(5) ^ flitReg(6) ){
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arbLock := "b1".U(16.W) << 7
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} .elsewhen( flitReg(6) ^ flitReg(7) ){
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arbLock := "b1".U(16.W) << 8
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} .elsewhen( flitReg(7) ^ flitReg(8) ){
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arbLock := "b1".U(16.W) << 9
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} .elsewhen( flitReg(8) ^ flitReg(9) ){
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arbLock := "b1".U(16.W) << 10
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} .elsewhen( flitReg(9) ^ flitReg(10) ){
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arbLock := "b1".U(16.W) << 11
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} .elsewhen( flitReg(10) ^ flitReg(11) ){
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arbLock := "b1".U(16.W) << 12
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} .elsewhen( flitReg(11) ^ flitReg(12) ){
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arbLock := "b1".U(16.W) << 13
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} .elsewhen( flitReg(12) ^ flitReg(13) ){
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arbLock := "b1".U(16.W) << 14
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} .elsewhen( flitReg(13) ^ flitReg(14) ){
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arbLock := "b1".U(16.W) << 15
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} .elsewhen( flitReg(14) ^ flitReg(15) ){
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arbLock := "b1".U(16.W) << 0
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} .elsewhen( flitReg(15) ^ flitReg(0) ){
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arbLock := "b1".U(16.W) << 1
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when( ~isLock ){
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for( i <- 0 until clkNum ){
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val j = clkNum - i -1
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when( flitReg(j) ^ flitReg(j+1) ){
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arbLock := "b1".U(clkNum.W) << j
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isLock := true.B
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}
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}
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} .elsewhen( clearCnt === 10.U ){
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isLock := false.B
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}
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val asyncSerDat =
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Mux1H(
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(for { i <- 0 until clkNum } yield {
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(arbLock === (1.U << i)) -> flitReg(i)
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(arbLock === (1.U << i)) -> flitReg(i+(clkNum/2))
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})
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)
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syncSerDat := ShiftRegister( asyncSerDat, 2 )
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syncSerDat := asyncSerDat
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}
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@@ -245,7 +237,9 @@ trait CDRInAxis{ this: CDRInBase =>
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class CDRIn extends CDRInBase
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with CDRInAxis
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with CDRInOverSample
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with CDRInOverSample{
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require(false)
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}
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class MPCDRIn extends CDRInBase
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with CDRInAxis
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