From b0b221e8b031d510e68a68a44ebd2cd7d49f49c9 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Mon, 11 Aug 2025 18:13:58 +0800
Subject: [PATCH 01/15] =?UTF-8?q?16=E7=9B=B8=E4=BD=8D=E6=93=8D=E4=BD=9C?=
 =?UTF-8?q?=E8=BF=98=E6=98=AF=E5=8D=A1?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala | 81 +++--------------------
 1 file changed, 11 insertions(+), 70 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 49c0602..1f3a0f1 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -72,82 +72,23 @@ trait CDRInMultiSample{ this: CDRInBase =>
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
   val multiCLK = IO(Input(Vec(16, Bool())))
 
-  // val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
-  val sampleReg = for( i <- 0 until 16 ) yield {
-    withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
+
+  val sampleReg = Wire(Vec(23, Bool()))
+  
+  for( i <- 0 until 16 ) {
+    sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
+  }
+  for( i <- 16 until 23 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
   }
 
 
-  val flitReg =
-  if(false){
-    for( i <- 0 until 16 ) yield {
-      sampleReg(i)
-    }
-  } else if (true){ //5选3 多数投票 滤波
-    for( i <- 0 until 16 ) yield {
-      (sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
-      (sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
-      (sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+2)%16)) |
-      (sampleReg((i-2+16)%16) & sampleReg((i+0)%16)    & sampleReg((i+1)%16)) |
-      (sampleReg((i-2+16)%16) & sampleReg((i+0)%16)    & sampleReg((i+2)%16)) |
-      (sampleReg((i-2+16)%16) & sampleReg((i+1)%16)    & sampleReg((i+2)%16)) |
-      (sampleReg((i-1+16)%16) & sampleReg((i+0)%16)    & sampleReg((i+1)%16)) |
-      (sampleReg((i-1+16)%16) & sampleReg((i+0)%16)    & sampleReg((i+2)%16)) |
-      (sampleReg((i-1+16)%16) & sampleReg((i+1)%16)    & sampleReg((i+2)%16)) |
-      (sampleReg((i-0)%16)    & sampleReg((i+1)%16)    & sampleReg((i+2)%16))
-    }
-  } else { //3选2 多数投票 滤波
-    for( i <- 0 until 16 ) yield {
-      (sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
-      (sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
-      (sampleReg((i+0)%16)    & sampleReg((i+1)%16))
-    }
-  }
+
+  val asyncSerDat = PopCount(sampleReg) >= 12.U
 
 
-  val arbLock = Reg(UInt( 16.W ))
+    // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
 
-  //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
-  when( flitReg(0) ^ flitReg(1) ){
-    arbLock := "b1".U(16.W) << 2
-  } .elsewhen( flitReg(1) ^ flitReg(2) ){
-    arbLock := "b1".U(16.W) << 3
-  } .elsewhen( flitReg(2) ^ flitReg(3) ){
-    arbLock := "b1".U(16.W) << 4
-  } .elsewhen( flitReg(3) ^ flitReg(4) ){
-    arbLock := "b1".U(16.W) << 5
-  } .elsewhen( flitReg(4) ^ flitReg(5) ){
-    arbLock := "b1".U(16.W) << 6
-  } .elsewhen( flitReg(5) ^ flitReg(6) ){
-    arbLock := "b1".U(16.W) << 7
-  } .elsewhen( flitReg(6) ^ flitReg(7) ){
-    arbLock := "b1".U(16.W) << 8
-  } .elsewhen( flitReg(7) ^ flitReg(8) ){
-    arbLock := "b1".U(16.W) << 9
-  } .elsewhen( flitReg(8) ^ flitReg(9) ){
-    arbLock := "b1".U(16.W) << 10
-  } .elsewhen( flitReg(9) ^ flitReg(10) ){
-    arbLock := "b1".U(16.W) << 11
-  } .elsewhen( flitReg(10) ^ flitReg(11) ){
-    arbLock := "b1".U(16.W) << 12
-  } .elsewhen( flitReg(11) ^ flitReg(12) ){
-    arbLock := "b1".U(16.W) << 13
-  } .elsewhen( flitReg(12) ^ flitReg(13) ){
-    arbLock := "b1".U(16.W) << 14
-  } .elsewhen( flitReg(13) ^ flitReg(14) ){
-    arbLock := "b1".U(16.W) << 15
-  } .elsewhen( flitReg(14) ^ flitReg(15) ){
-    arbLock := "b1".U(16.W) << 0
-  } .elsewhen( flitReg(15) ^ flitReg(0) ){
-    arbLock := "b1".U(16.W) << 1
-  } 
-
-  val asyncSerDat = 
-    Mux1H(
-      (for { i <- 0 until clkNum } yield {
-        (arbLock === (1.U << i)) -> flitReg(i)
-      })
-    )
 
   syncSerDat := ShiftRegister( asyncSerDat, 2 )
 

From 7338314c17f30443b0d761b3b8ec9f6d96b26402 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Mon, 11 Aug 2025 19:33:56 +0800
Subject: [PATCH 02/15] =?UTF-8?q?4=E5=A4=9A=E7=9B=B8=E4=BD=8D=E6=95=88?=
 =?UTF-8?q?=E6=9E=9C=E6=98=8E=E6=98=BE=E6=9B=B4=E5=A5=BD?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 12 ++++++------
 src/main/scala/backBoard/shin/ShinTop.scala |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 1f3a0f1..222c451 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(16, Bool())))
+  val multiCLK = IO(Input(Vec(4, Bool())))
 
 
-  val sampleReg = Wire(Vec(23, Bool()))
+  val sampleReg = Wire(Vec(5, Bool()))
   
-  for( i <- 0 until 16 ) {
+  for( i <- 0 until 4 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 16 until 23 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
+  for( i <- 4 until 5 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-1).asClock, reset.asBool){ RegNext(sampleReg(i-1))}
   }
 
 
 
-  val asyncSerDat = PopCount(sampleReg) >= 12.U
+  val asyncSerDat = PopCount(sampleReg) >= 3.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 45638a1..d5513d4 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(16, Bool()))
+  val multiCLK = Input(Vec(4, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO

From 107895f6e002052d825c97d202d0c42325bf9dd2 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Tue, 12 Aug 2025 09:55:43 +0800
Subject: [PATCH 03/15] =?UTF-8?q?Revert=20"4=E5=A4=9A=E7=9B=B8=E4=BD=8D?=
 =?UTF-8?q?=E6=95=88=E6=9E=9C=E6=98=8E=E6=98=BE=E6=9B=B4=E5=A5=BD"?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit 7338314c17f30443b0d761b3b8ec9f6d96b26402.
---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 12 ++++++------
 src/main/scala/backBoard/shin/ShinTop.scala |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 222c451..1f3a0f1 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(4, Bool())))
+  val multiCLK = IO(Input(Vec(16, Bool())))
 
 
-  val sampleReg = Wire(Vec(5, Bool()))
+  val sampleReg = Wire(Vec(23, Bool()))
   
-  for( i <- 0 until 4 ) {
+  for( i <- 0 until 16 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 4 until 5 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-1).asClock, reset.asBool){ RegNext(sampleReg(i-1))}
+  for( i <- 16 until 23 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
   }
 
 
 
-  val asyncSerDat = PopCount(sampleReg) >= 3.U
+  val asyncSerDat = PopCount(sampleReg) >= 12.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index d5513d4..45638a1 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(4, Bool()))
+  val multiCLK = Input(Vec(16, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO

From cb2c4f46e5db48116cb19638fa49562bc632ca86 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Tue, 12 Aug 2025 17:48:35 +0800
Subject: [PATCH 04/15] =?UTF-8?q?=E6=8B=89=E5=87=BA=E6=B5=8B=E8=AF=95IO?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 4 +++-
 src/main/scala/backBoard/shin/ShinTop.scala | 8 +++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 1f3a0f1..6290a81 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -65,7 +65,7 @@ trait CDRInOverSample{ this: CDRInBase =>
 }
 
 trait CDRInMultiSample{ this: CDRInBase =>
-  
+  val testIO = IO(Output(UInt(3.W)))
   val clkNum: Int = 16
 
 
@@ -92,6 +92,8 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
   syncSerDat := ShiftRegister( asyncSerDat, 2 )
 
+
+  testIO := Cat( syncSerDat, asyncSerDat, io.serDat )
 }
 
 
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 45638a1..f8aa6ad 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -36,6 +36,8 @@ class ShinTopIO extends Bundle{
   val pllCtrl = Output(UInt(32.W))
   val xtal    = Output(UInt(12.W))
   val spiSel  = Output(UInt(2.W))
+
+  val testIO = Output(UInt(12.W))
 }
 
 
@@ -73,7 +75,11 @@ abstract class ShinTopBase extends Module{
   interface.io.intTransEnd(3) := upCDROut.io.axis.fire   & upCDROut.io.axis.bits.tlast
 
   io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
-  
+
+  io.testIO := Cat(
+    upCDROut.io.serDat, upCDRIn.testIO, downCDROut.io.serDat, downCDRIn.testIO, clock.asBool
+  )
+
   io.isSoftReset := interface.io.isSoftReset
   io.interrupt   := interface.io.interrupt
 

From 495a238a2650aac526ae5d25a6a3a4298d8e5c81 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 13 Aug 2025 10:00:11 +0800
Subject: [PATCH 05/15] =?UTF-8?q?=E6=94=B96=E7=9B=B8=E4=BD=8D=EF=BC=8C?=
 =?UTF-8?q?=E4=BB=8E=E4=B8=80=E4=B8=AApll=E5=87=BA=EF=BC=8C=E6=B5=8B?=
 =?UTF-8?q?=E8=AF=95?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 12 ++++++------
 src/main/scala/backBoard/shin/ShinTop.scala |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 6290a81..625389a 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(16, Bool())))
+  val multiCLK = IO(Input(Vec(6, Bool())))
 
 
-  val sampleReg = Wire(Vec(23, Bool()))
+  val sampleReg = Wire(Vec(9, Bool()))
   
-  for( i <- 0 until 16 ) {
+  for( i <- 0 until 6 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 16 until 23 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
+  for( i <- 6 until 9 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-3).asClock, reset.asBool){ RegNext(sampleReg(i-3))}
   }
 
 
 
-  val asyncSerDat = PopCount(sampleReg) >= 12.U
+  val asyncSerDat = PopCount(sampleReg) >= 5.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index f8aa6ad..a482e1c 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(16, Bool()))
+  val multiCLK = Input(Vec(6, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO

From c6aa7416fc6b66778bdf080f7a381ed7343a5d25 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 13 Aug 2025 10:52:49 +0800
Subject: [PATCH 06/15] =?UTF-8?q?=E5=B0=9D=E8=AF=953=E7=9B=B8=E4=BD=8D?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 12 ++++++------
 src/main/scala/backBoard/shin/ShinTop.scala |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 625389a..90f3ffa 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(6, Bool())))
+  val multiCLK = IO(Input(Vec(3, Bool())))
 
 
-  val sampleReg = Wire(Vec(9, Bool()))
+  val sampleReg = Wire(Vec(5, Bool()))
   
-  for( i <- 0 until 6 ) {
+  for( i <- 0 until 3 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 6 until 9 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-3).asClock, reset.asBool){ RegNext(sampleReg(i-3))}
+  for( i <- 3 until 5 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-2).asClock, reset.asBool){ RegNext(sampleReg(i-2))}
   }
 
 
 
-  val asyncSerDat = PopCount(sampleReg) >= 5.U
+  val asyncSerDat = PopCount(sampleReg) >= 3.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index a482e1c..cddf0f9 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(6, Bool()))
+  val multiCLK = Input(Vec(3, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO

From 4955b7a278a092a0be1f59df71dc08acad480de6 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 13 Aug 2025 17:54:39 +0800
Subject: [PATCH 07/15] =?UTF-8?q?Revert=20"=E5=B0=9D=E8=AF=953=E7=9B=B8?=
 =?UTF-8?q?=E4=BD=8D"?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit c6aa7416fc6b66778bdf080f7a381ed7343a5d25.
---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 12 ++++++------
 src/main/scala/backBoard/shin/ShinTop.scala |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 90f3ffa..625389a 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(3, Bool())))
+  val multiCLK = IO(Input(Vec(6, Bool())))
 
 
-  val sampleReg = Wire(Vec(5, Bool()))
+  val sampleReg = Wire(Vec(9, Bool()))
   
-  for( i <- 0 until 3 ) {
+  for( i <- 0 until 6 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 3 until 5 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-2).asClock, reset.asBool){ RegNext(sampleReg(i-2))}
+  for( i <- 6 until 9 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-3).asClock, reset.asBool){ RegNext(sampleReg(i-3))}
   }
 
 
 
-  val asyncSerDat = PopCount(sampleReg) >= 3.U
+  val asyncSerDat = PopCount(sampleReg) >= 5.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index cddf0f9..a482e1c 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(3, Bool()))
+  val multiCLK = Input(Vec(6, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO

From 035109bee16892a6439c7a383b7fa05926912141 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 13 Aug 2025 17:54:50 +0800
Subject: [PATCH 08/15] =?UTF-8?q?Revert=20"=E6=94=B96=E7=9B=B8=E4=BD=8D?=
 =?UTF-8?q?=EF=BC=8C=E4=BB=8E=E4=B8=80=E4=B8=AApll=E5=87=BA=EF=BC=8C?=
 =?UTF-8?q?=E6=B5=8B=E8=AF=95"?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit 495a238a2650aac526ae5d25a6a3a4298d8e5c81.
---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 12 ++++++------
 src/main/scala/backBoard/shin/ShinTop.scala |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 625389a..6290a81 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(6, Bool())))
+  val multiCLK = IO(Input(Vec(16, Bool())))
 
 
-  val sampleReg = Wire(Vec(9, Bool()))
+  val sampleReg = Wire(Vec(23, Bool()))
   
-  for( i <- 0 until 6 ) {
+  for( i <- 0 until 16 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 6 until 9 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-3).asClock, reset.asBool){ RegNext(sampleReg(i-3))}
+  for( i <- 16 until 23 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
   }
 
 
 
-  val asyncSerDat = PopCount(sampleReg) >= 5.U
+  val asyncSerDat = PopCount(sampleReg) >= 12.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index a482e1c..f8aa6ad 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(6, Bool()))
+  val multiCLK = Input(Vec(16, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO

From fc917054ed49fa3132309c4e01423207efe1fda8 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Thu, 14 Aug 2025 19:20:49 +0800
Subject: [PATCH 09/15] =?UTF-8?q?bug:=2016=E7=9B=B8=E4=BD=8D=E8=A1=A5?=
 =?UTF-8?q?=E5=85=85=E7=9B=B8=20=E6=AC=A0=E4=BA=86=E4=B8=80=E7=9B=B8?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 6290a81..991b743 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -79,7 +79,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
   for( i <- 16 until 23 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
+    sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))}
   }
 
 

From 2da45138db34e6ea8c8432d7cebfcd8870d2933a Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Fri, 15 Aug 2025 10:45:10 +0800
Subject: [PATCH 10/15] =?UTF-8?q?16=E7=9B=B8=E4=BD=8D=E6=94=B98=E7=9B=B8?=
 =?UTF-8?q?=E4=BD=8D?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 12 ++++++------
 src/main/scala/backBoard/shin/ShinTop.scala |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 991b743..d0310a6 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(16, Bool())))
+  val multiCLK = IO(Input(Vec(8, Bool())))
 
 
-  val sampleReg = Wire(Vec(23, Bool()))
+  val sampleReg = Wire(Vec(11, Bool()))
   
-  for( i <- 0 until 16 ) {
+  for( i <- 0 until 8 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 16 until 23 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))}
+  for( i <- 8 until 11 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-4+1).asClock, reset.asBool){ RegNext(sampleReg(i-4+1))}
   }
 
 
 
-  val asyncSerDat = PopCount(sampleReg) >= 12.U
+  val asyncSerDat = PopCount(sampleReg) >= 6.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index f8aa6ad..0f5a83d 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(16, Bool()))
+  val multiCLK = Input(Vec(8, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO

From 62684bd66572cbff4453d0d9b1b698c78f9d0448 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Fri, 15 Aug 2025 10:45:44 +0800
Subject: [PATCH 11/15] =?UTF-8?q?Revert=20"16=E7=9B=B8=E4=BD=8D=E6=94=B98?=
 =?UTF-8?q?=E7=9B=B8=E4=BD=8D"?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit 2da45138db34e6ea8c8432d7cebfcd8870d2933a.
---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 12 ++++++------
 src/main/scala/backBoard/shin/ShinTop.scala |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index d0310a6..991b743 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(8, Bool())))
+  val multiCLK = IO(Input(Vec(16, Bool())))
 
 
-  val sampleReg = Wire(Vec(11, Bool()))
+  val sampleReg = Wire(Vec(23, Bool()))
   
-  for( i <- 0 until 8 ) {
+  for( i <- 0 until 16 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 8 until 11 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-4+1).asClock, reset.asBool){ RegNext(sampleReg(i-4+1))}
+  for( i <- 16 until 23 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))}
   }
 
 
 
-  val asyncSerDat = PopCount(sampleReg) >= 6.U
+  val asyncSerDat = PopCount(sampleReg) >= 12.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 0f5a83d..f8aa6ad 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(8, Bool()))
+  val multiCLK = Input(Vec(16, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO

From 45d2d223c1f620d8370013fb920b7f6d01aabd36 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Fri, 15 Aug 2025 15:28:28 +0800
Subject: [PATCH 12/15] =?UTF-8?q?enhance=20=E8=A6=81=E6=B1=82=E5=85=88?=
 =?UTF-8?q?=E8=B7=A8=E6=97=B6=E9=92=9F=EF=BC=8C=E5=86=8D=E8=BF=9B=E8=A1=8C?=
 =?UTF-8?q?=E5=90=8E=E7=BB=AD=E8=A1=A8=E5=86=B3?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 991b743..1fe1c83 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -73,18 +73,24 @@ trait CDRInMultiSample{ this: CDRInBase =>
   val multiCLK = IO(Input(Vec(16, Bool())))
 
 
-  val sampleReg = Wire(Vec(23, Bool()))
+  val sampleReg = Wire(Vec(16, Bool()))
   
   for( i <- 0 until 16 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 16 until 23 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))}
+
+  val sampleReg_sync = Wire(Vec(23,Bool()))
+
+  for( i <- 0 until 7 ){
+    sampleReg_sync(i) := RegNext(sampleReg_sync(i+15))
+  }
+
+  for( i <- 7 until 23 ){
+    sampleReg_sync(i) := RegNext(sampleReg(i-7))
   }
 
 
-
-  val asyncSerDat = PopCount(sampleReg) >= 12.U
+  val asyncSerDat = PopCount(sampleReg_sync) >= 12.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U

From 11bbf14226ae5f9230b10507a5cb2f13f47786a2 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Fri, 15 Aug 2025 17:18:45 +0800
Subject: [PATCH 13/15] =?UTF-8?q?=E6=BB=A4=E6=B3=A2=20=E8=A1=A8=E5=86=B3?=
 =?UTF-8?q?=20=E9=89=B4=E7=9B=B8=E5=90=8C=E6=97=B6=E5=AD=98=E5=9C=A8?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala | 67 ++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 1fe1c83..76d4089 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -90,13 +90,74 @@ trait CDRInMultiSample{ this: CDRInBase =>
   }
 
 
-  val asyncSerDat = PopCount(sampleReg_sync) >= 12.U
+// val flitReg =
+//   for( i <- 1 until 22 ) yield {
+//     (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+//     (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+//     (sampleReg_sync(i+0) & sampleReg_sync(i+1))
+//   }
 
 
-    // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
+
+  // val asyncSerDat = PopCount(flitReg) >= 11.U
 
 
-  syncSerDat := ShiftRegister( asyncSerDat, 2 )
+val flitReg =
+  for( i <- 6 until 22 ) yield {
+    (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+    (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+    (sampleReg_sync(i+0) & sampleReg_sync(i+1))
+  }
+
+
+val arbLock = Reg(UInt( 16.W ))
+
+  //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
+  when( flitReg(0) ^ flitReg(1) ){
+    arbLock := "b1".U(16.W) << 7
+  } .elsewhen( flitReg(1) ^ flitReg(2) ){
+    arbLock := "b1".U(16.W) << 8
+  } .elsewhen( flitReg(2) ^ flitReg(3) ){
+    arbLock := "b1".U(16.W) << 9
+  } .elsewhen( flitReg(3) ^ flitReg(4) ){
+    arbLock := "b1".U(16.W) << 10
+  } .elsewhen( flitReg(4) ^ flitReg(5) ){
+    arbLock := "b1".U(16.W) << 11
+  } .elsewhen( flitReg(5) ^ flitReg(6) ){
+    arbLock := "b1".U(16.W) << 12
+  } .elsewhen( flitReg(6) ^ flitReg(7) ){
+    arbLock := "b1".U(16.W) << 13
+  } .elsewhen( flitReg(7) ^ flitReg(8) ){
+    arbLock := "b1".U(16.W) << 14
+  } .elsewhen( flitReg(8) ^ flitReg(9) ){
+    arbLock := "b1".U(16.W) << 15
+  } .elsewhen( flitReg(9) ^ flitReg(10) ){
+    arbLock := "b1".U(16.W) << 0
+  } .elsewhen( flitReg(10) ^ flitReg(11) ){
+    arbLock := "b1".U(16.W) << 1
+  } .elsewhen( flitReg(11) ^ flitReg(12) ){
+    arbLock := "b1".U(16.W) << 2
+  } .elsewhen( flitReg(12) ^ flitReg(13) ){
+    arbLock := "b1".U(16.W) << 3
+  } .elsewhen( flitReg(13) ^ flitReg(14) ){
+    arbLock := "b1".U(16.W) << 4
+  } .elsewhen( flitReg(14) ^ flitReg(15) ){
+    arbLock := "b1".U(16.W) << 5
+  } .elsewhen( flitReg(15) ^ flitReg(0) ){
+    arbLock := "b1".U(16.W) << 6
+  } 
+
+  val asyncSerDat = 
+    Mux1H(
+      (for { i <- 0 until clkNum } yield {
+        (arbLock === (1.U << i)) -> flitReg(i)
+      })
+    )
+
+
+
+
+  syncSerDat := asyncSerDat //ShiftRegister( asyncSerDat, 2 )
 
 
   testIO := Cat( syncSerDat, asyncSerDat, io.serDat )

From 2afd3f722ae1bee1d7659a474e749e15686a155b Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Mon, 18 Aug 2025 16:20:50 +0800
Subject: [PATCH 14/15] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=B8=80=E4=B8=AA?=
 =?UTF-8?q?=E9=94=81=E5=AE=9A=E5=8F=AF=E4=BB=A5=E6=9A=82=E6=97=B6=E8=A7=A3?=
 =?UTF-8?q?=E5=86=B3=E5=8F=91=E9=80=81=E5=A4=B1=E8=B4=A5=E9=97=AE=E9=A2=98?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 136 ++++++++++----------
 src/main/scala/backBoard/shin/ShinTop.scala |   4 +-
 2 files changed, 70 insertions(+), 70 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 76d4089..e63b08f 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -17,6 +17,12 @@ abstract class CDRInBase extends Module{
 
   val io: CDRInIO = IO(new CDRInIO)
 
+  val STATE_IDLE = 0.U
+  val STATE_HEADER = 1.U
+  val STATE_PAYLOAD = 2.U
+
+  val stateNext = Wire(UInt(2.W))
+  val stateCurr = RegNext( stateNext, STATE_IDLE )
 
   val syncSerDat = Wire(Bool())
 }
@@ -65,92 +71,91 @@ trait CDRInOverSample{ this: CDRInBase =>
 }
 
 trait CDRInMultiSample{ this: CDRInBase =>
-  val testIO = IO(Output(UInt(3.W)))
+  val testIO = IO(Output(UInt(10.W)))
   val clkNum: Int = 16
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(16, Bool())))
+  val multiCLK = IO(Input(Vec(8, Bool())))
 
 
-  val sampleReg = Wire(Vec(16, Bool()))
+  val sampleReg = Wire(Vec(8, Bool()))
   
-  for( i <- 0 until 16 ) {
+  for( i <- 0 until 8 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
 
-  val sampleReg_sync = Wire(Vec(23,Bool()))
+  val sampleReg_sync = Wire(Vec(16,Bool()))
 
-  for( i <- 0 until 7 ){
-    sampleReg_sync(i) := RegNext(sampleReg_sync(i+15))
+
+
+  for( i <- 0 until 8 ){
+    sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
   }
 
-  for( i <- 7 until 23 ){
-    sampleReg_sync(i) := RegNext(sampleReg(i-7))
+  for( i <- 8 until 16 ){
+    sampleReg_sync(i) := ShiftRegister(sampleReg(i-8), 1)
   }
 
+  /*
+  val flitReg =
+    for( i <- 1 until 22 ) yield {
+      (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+      (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+      (sampleReg_sync(i+0) & sampleReg_sync(i+1))
+    }
 
-// val flitReg =
-//   for( i <- 1 until 22 ) yield {
-//     (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
-//     (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
-//     (sampleReg_sync(i+0) & sampleReg_sync(i+1))
-//   }
+  val asyncSerDat = PopCount(flitReg) >= 11.U
+  */
+
+  val flitReg =
+    for( i <- 1 until 15 ) yield {
+      (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+      (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+      (sampleReg_sync(i+0) & sampleReg_sync(i+1))
+    }
 
 
+  val arbLock = Reg(UInt( 8.W ))
+  val isLock = RegInit(false.B)
 
-  // val asyncSerDat = PopCount(flitReg) >= 11.U
-
-
-val flitReg =
-  for( i <- 6 until 22 ) yield {
-    (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
-    (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
-    (sampleReg_sync(i+0) & sampleReg_sync(i+1))
-  }
-
-
-val arbLock = Reg(UInt( 16.W ))
 
   //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
-  when( flitReg(0) ^ flitReg(1) ){
-    arbLock := "b1".U(16.W) << 7
-  } .elsewhen( flitReg(1) ^ flitReg(2) ){
-    arbLock := "b1".U(16.W) << 8
-  } .elsewhen( flitReg(2) ^ flitReg(3) ){
-    arbLock := "b1".U(16.W) << 9
-  } .elsewhen( flitReg(3) ^ flitReg(4) ){
-    arbLock := "b1".U(16.W) << 10
-  } .elsewhen( flitReg(4) ^ flitReg(5) ){
-    arbLock := "b1".U(16.W) << 11
-  } .elsewhen( flitReg(5) ^ flitReg(6) ){
-    arbLock := "b1".U(16.W) << 12
-  } .elsewhen( flitReg(6) ^ flitReg(7) ){
-    arbLock := "b1".U(16.W) << 13
-  } .elsewhen( flitReg(7) ^ flitReg(8) ){
-    arbLock := "b1".U(16.W) << 14
-  } .elsewhen( flitReg(8) ^ flitReg(9) ){
-    arbLock := "b1".U(16.W) << 15
-  } .elsewhen( flitReg(9) ^ flitReg(10) ){
-    arbLock := "b1".U(16.W) << 0
-  } .elsewhen( flitReg(10) ^ flitReg(11) ){
-    arbLock := "b1".U(16.W) << 1
-  } .elsewhen( flitReg(11) ^ flitReg(12) ){
-    arbLock := "b1".U(16.W) << 2
-  } .elsewhen( flitReg(12) ^ flitReg(13) ){
-    arbLock := "b1".U(16.W) << 3
-  } .elsewhen( flitReg(13) ^ flitReg(14) ){
-    arbLock := "b1".U(16.W) << 4
-  } .elsewhen( flitReg(14) ^ flitReg(15) ){
-    arbLock := "b1".U(16.W) << 5
-  } .elsewhen( flitReg(15) ^ flitReg(0) ){
-    arbLock := "b1".U(16.W) << 6
-  } 
+  when( ~isLock ){
+    when( flitReg(0) ^ flitReg(1) ){
+      arbLock := "b1".U(16.W) << 0
+      isLock := true.B
+    } .elsewhen( flitReg(1) ^ flitReg(2) ){
+      arbLock := "b1".U(16.W) << 1
+      isLock := true.B
+    } .elsewhen( flitReg(2) ^ flitReg(3) ){
+      arbLock := "b1".U(16.W) << 2
+      isLock := true.B
+    } .elsewhen( flitReg(3) ^ flitReg(4) ){
+      arbLock := "b1".U(16.W) << 3
+      isLock := true.B
+    } .elsewhen( flitReg(4) ^ flitReg(5) ){
+      arbLock := "b1".U(16.W) << 4
+      isLock := true.B
+    } .elsewhen( flitReg(5) ^ flitReg(6) ){
+      arbLock := "b1".U(16.W) << 5
+      isLock := true.B
+    } .elsewhen( flitReg(6) ^ flitReg(7) ){
+      arbLock := "b1".U(16.W) << 6
+      isLock := true.B
+    } .elsewhen( flitReg(7) ^ flitReg(8) ){
+      arbLock := "b1".U(16.W) << 7
+      isLock := true.B
+    }
+  } .elsewhen( stateNext === STATE_IDLE & stateCurr === STATE_PAYLOAD ){
+    isLock := false.B
+  }
+
 
   val asyncSerDat = 
     Mux1H(
-      (for { i <- 0 until clkNum } yield {
-        (arbLock === (1.U << i)) -> flitReg(i)
+      (for { i <- 0 until 8 } yield {
+        (arbLock === (1.U << i)) -> flitReg(i+4)
       })
     )
 
@@ -160,7 +165,7 @@ val arbLock = Reg(UInt( 16.W ))
   syncSerDat := asyncSerDat //ShiftRegister( asyncSerDat, 2 )
 
 
-  testIO := Cat( syncSerDat, asyncSerDat, io.serDat )
+  testIO := Cat( syncSerDat, Cat(flitReg), io.serDat )
 }
 
 
@@ -172,12 +177,7 @@ trait CDRInAxis{ this: CDRInBase =>
   val ETH_PRE = "b1100010001".U(10.W)
   val ETH_SFD = "b0110100111".U(10.W)
 
-  val STATE_IDLE = 0.U
-  val STATE_HEADER = 1.U
-  val STATE_PAYLOAD = 2.U
 
-  val stateNext = Wire(UInt(2.W))
-  val stateCurr = RegNext( stateNext, STATE_IDLE )
 
   val bitCnt = Reg(UInt(4.W))
   val byteCnt = RegInit(0.U((12+1).W))
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index f8aa6ad..818521f 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(16, Bool()))
+  val multiCLK = Input(Vec(8, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO
@@ -77,7 +77,7 @@ abstract class ShinTopBase extends Module{
   io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
 
   io.testIO := Cat(
-    upCDROut.io.serDat, upCDRIn.testIO, downCDROut.io.serDat, downCDRIn.testIO, clock.asBool
+    downCDROut.io.serDat, downCDRIn.testIO, clock.asBool
   )
 
   io.isSoftReset := interface.io.isSoftReset

From 2fb450673f5fb9c9bba4b39266ac1d2f96f49884 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Mon, 18 Aug 2025 17:39:32 +0800
Subject: [PATCH 15/15] =?UTF-8?q?=E8=B0=83=E6=95=B4=E8=A7=A3=E9=94=81?=
 =?UTF-8?q?=E6=9D=A1=E4=BB=B6=E4=B8=BA10=E4=B8=AA=E8=BF=9E=E7=BB=AD0?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 88 +++++++++------------
 src/main/scala/backBoard/shin/ShinTop.scala |  7 +-
 2 files changed, 38 insertions(+), 57 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index e63b08f..be04b28 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -17,14 +17,7 @@ abstract class CDRInBase extends Module{
 
   val io: CDRInIO = IO(new CDRInIO)
 
-  val STATE_IDLE = 0.U
-  val STATE_HEADER = 1.U
-  val STATE_PAYLOAD = 2.U
-
-  val stateNext = Wire(UInt(2.W))
-  val stateCurr = RegNext( stateNext, STATE_IDLE )
-
-  val syncSerDat = Wire(Bool())
+    val syncSerDat = Wire(Bool())
 }
 
 trait CDRInOverSample{ this: CDRInBase =>
@@ -71,30 +64,30 @@ trait CDRInOverSample{ this: CDRInBase =>
 }
 
 trait CDRInMultiSample{ this: CDRInBase =>
-  val testIO = IO(Output(UInt(10.W)))
   val clkNum: Int = 16
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(8, Bool())))
+  val multiCLK = IO(Input(Vec(clkNum, Bool())))
 
 
-  val sampleReg = Wire(Vec(8, Bool()))
+
+  val sampleReg = Wire(Vec(clkNum, Bool()))
   
-  for( i <- 0 until 8 ) {
+  for( i <- 0 until clkNum ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
 
-  val sampleReg_sync = Wire(Vec(16,Bool()))
+  val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
 
 
 
-  for( i <- 0 until 8 ){
+  for( i <- 0 until clkNum ){
     sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
   }
 
-  for( i <- 8 until 16 ){
-    sampleReg_sync(i) := ShiftRegister(sampleReg(i-8), 1)
+  for( i <- clkNum until 2*clkNum ){
+    sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1)
   }
 
   /*
@@ -109,63 +102,49 @@ trait CDRInMultiSample{ this: CDRInBase =>
   */
 
   val flitReg =
-    for( i <- 1 until 15 ) yield {
+    for( i <- 1 until (2*clkNum)-1 ) yield {
       (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
       (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
       (sampleReg_sync(i+0) & sampleReg_sync(i+1))
     }
 
-
-  val arbLock = Reg(UInt( 8.W ))
+  val clearCnt = Reg(UInt(4.W))
+  val arbLock = Reg(UInt( clkNum.W ))
   val isLock = RegInit(false.B)
 
+  when( sampleReg.reduce(_|_) === false.B ){
+    when( clearCnt =/= 10.U ){
+      clearCnt := clearCnt + 1.U
+    }
+  } .otherwise{
+    clearCnt := 0.U
+  }
+
 
   //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
   when( ~isLock ){
-    when( flitReg(0) ^ flitReg(1) ){
-      arbLock := "b1".U(16.W) << 0
-      isLock := true.B
-    } .elsewhen( flitReg(1) ^ flitReg(2) ){
-      arbLock := "b1".U(16.W) << 1
-      isLock := true.B
-    } .elsewhen( flitReg(2) ^ flitReg(3) ){
-      arbLock := "b1".U(16.W) << 2
-      isLock := true.B
-    } .elsewhen( flitReg(3) ^ flitReg(4) ){
-      arbLock := "b1".U(16.W) << 3
-      isLock := true.B
-    } .elsewhen( flitReg(4) ^ flitReg(5) ){
-      arbLock := "b1".U(16.W) << 4
-      isLock := true.B
-    } .elsewhen( flitReg(5) ^ flitReg(6) ){
-      arbLock := "b1".U(16.W) << 5
-      isLock := true.B
-    } .elsewhen( flitReg(6) ^ flitReg(7) ){
-      arbLock := "b1".U(16.W) << 6
-      isLock := true.B
-    } .elsewhen( flitReg(7) ^ flitReg(8) ){
-      arbLock := "b1".U(16.W) << 7
-      isLock := true.B
+    for( i <- 0 until clkNum ){
+      val j = clkNum - i -1
+      when( flitReg(j) ^ flitReg(j+1) ){
+        arbLock := "b1".U(clkNum.W) << j
+        isLock := true.B
+      }
     }
-  } .elsewhen( stateNext === STATE_IDLE & stateCurr === STATE_PAYLOAD ){
+  } .elsewhen( clearCnt === 10.U ){
     isLock := false.B
   }
 
 
   val asyncSerDat = 
     Mux1H(
-      (for { i <- 0 until 8 } yield {
-        (arbLock === (1.U << i)) -> flitReg(i+4)
+      (for { i <- 0 until clkNum } yield {
+        (arbLock === (1.U << i)) -> flitReg(i+(clkNum/2))
       })
     )
 
 
+  syncSerDat := asyncSerDat
 
-
-  syncSerDat := asyncSerDat //ShiftRegister( asyncSerDat, 2 )
-
-
-  testIO := Cat( syncSerDat, Cat(flitReg), io.serDat )
 }
 
 
@@ -177,6 +156,13 @@ trait CDRInAxis{ this: CDRInBase =>
   val ETH_PRE = "b1100010001".U(10.W)
   val ETH_SFD = "b0110100111".U(10.W)
 
+  val STATE_IDLE = 0.U
+  val STATE_HEADER = 1.U
+  val STATE_PAYLOAD = 2.U
+
+  val stateNext = Wire(UInt(2.W))
+  val stateCurr = RegNext( stateNext, STATE_IDLE )
+
 
 
   val bitCnt = Reg(UInt(4.W))
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 818521f..f50fff0 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(8, Bool()))
+  val multiCLK = Input(Vec(16, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO
@@ -37,7 +37,6 @@ class ShinTopIO extends Bundle{
   val xtal    = Output(UInt(12.W))
   val spiSel  = Output(UInt(2.W))
 
-  val testIO = Output(UInt(12.W))
 }
 
 
@@ -76,10 +75,6 @@ abstract class ShinTopBase extends Module{
 
   io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
 
-  io.testIO := Cat(
-    downCDROut.io.serDat, downCDRIn.testIO, clock.asBool
-  )
-
   io.isSoftReset := interface.io.isSoftReset
   io.interrupt   := interface.io.interrupt