diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index e78db95..7fe74d6 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,90 +70,82 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(16, Bool())))
+  val multiCLK = IO(Input(Vec(clkNum, Bool())))
 
-  // val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
-  val sampleReg = for( i <- 0 until 16 ) yield {
-    withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
+
+
+  val sampleReg = Wire(Vec(clkNum, Bool()))
+  
+  for( i <- 0 until clkNum ) {
+    sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
 
+  val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
+
+
+
+  for( i <- 0 until clkNum ){
+    sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
+  }
+
+  for( i <- clkNum until 2*clkNum ){
+    sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1)
+  }
+
+  /*
+  val flitReg =
+    for( i <- 1 until 22 ) yield {
+      (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+      (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+      (sampleReg_sync(i+0) & sampleReg_sync(i+1))
+    }
+
+  val asyncSerDat = PopCount(flitReg) >= 11.U
+  */
 
   val flitReg =
-  if(false){
-    for( i <- 0 until 16 ) yield {
-      sampleReg(i)
+    for( i <- 1 until (2*clkNum)-1 ) yield {
+      (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+      (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+      (sampleReg_sync(i+0) & sampleReg_sync(i+1))
     }
-  } else if (false){ //5选3 多数投票 滤波
-    for( i <- 0 until 16 ) yield {
-      withClockAndReset(multiCLK((i+3)%16).asClock, reset.asBool){ RegNext(
-        (sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
-        (sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
-        (sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+2)%16)) |
-        (sampleReg((i-2+16)%16) & sampleReg((i+0)%16)    & sampleReg((i+1)%16)) |
-        (sampleReg((i-2+16)%16) & sampleReg((i+0)%16)    & sampleReg((i+2)%16)) |
-        (sampleReg((i-2+16)%16) & sampleReg((i+1)%16)    & sampleReg((i+2)%16)) |
-        (sampleReg((i-1+16)%16) & sampleReg((i+0)%16)    & sampleReg((i+1)%16)) |
-        (sampleReg((i-1+16)%16) & sampleReg((i+0)%16)    & sampleReg((i+2)%16)) |
-        (sampleReg((i-1+16)%16) & sampleReg((i+1)%16)    & sampleReg((i+2)%16)) |
-        (sampleReg((i-0)%16)    & sampleReg((i+1)%16)    & sampleReg((i+2)%16))
-      )}
-    }
-  } else { //3选2 多数投票 滤波
-    for( i <- 0 until 16 ) yield {
-      withClockAndReset(multiCLK((i+2)%16).asClock, reset.asBool){ RegNext(
-        (sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
-        (sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
-        (sampleReg((i+0)%16)    & sampleReg((i+1)%16))
-      )}
+
+  val clearCnt = Reg(UInt(4.W))
+  val arbLock = Reg(UInt( clkNum.W ))
+  val isLock = RegInit(false.B)
+
+  when( sampleReg.reduce(_|_) === false.B ){
+    when( clearCnt =/= 10.U ){
+      clearCnt := clearCnt + 1.U
     }
+  } .otherwise{
+    clearCnt := 0.U
   }
 
 
-  val arbLock = Reg(UInt( 16.W ))
-
   //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
-  when( flitReg(0) ^ flitReg(1) ){
-    arbLock := "b1".U(16.W) << 2
-  } .elsewhen( flitReg(1) ^ flitReg(2) ){
-    arbLock := "b1".U(16.W) << 3
-  } .elsewhen( flitReg(2) ^ flitReg(3) ){
-    arbLock := "b1".U(16.W) << 4
-  } .elsewhen( flitReg(3) ^ flitReg(4) ){
-    arbLock := "b1".U(16.W) << 5
-  } .elsewhen( flitReg(4) ^ flitReg(5) ){
-    arbLock := "b1".U(16.W) << 6
-  } .elsewhen( flitReg(5) ^ flitReg(6) ){
-    arbLock := "b1".U(16.W) << 7
-  } .elsewhen( flitReg(6) ^ flitReg(7) ){
-    arbLock := "b1".U(16.W) << 8
-  } .elsewhen( flitReg(7) ^ flitReg(8) ){
-    arbLock := "b1".U(16.W) << 9
-  } .elsewhen( flitReg(8) ^ flitReg(9) ){
-    arbLock := "b1".U(16.W) << 10
-  } .elsewhen( flitReg(9) ^ flitReg(10) ){
-    arbLock := "b1".U(16.W) << 11
-  } .elsewhen( flitReg(10) ^ flitReg(11) ){
-    arbLock := "b1".U(16.W) << 12
-  } .elsewhen( flitReg(11) ^ flitReg(12) ){
-    arbLock := "b1".U(16.W) << 13
-  } .elsewhen( flitReg(12) ^ flitReg(13) ){
-    arbLock := "b1".U(16.W) << 14
-  } .elsewhen( flitReg(13) ^ flitReg(14) ){
-    arbLock := "b1".U(16.W) << 15
-  } .elsewhen( flitReg(14) ^ flitReg(15) ){
-    arbLock := "b1".U(16.W) << 0
-  } .elsewhen( flitReg(15) ^ flitReg(0) ){
-    arbLock := "b1".U(16.W) << 1
-  } 
+  when( ~isLock ){
+    for( i <- 0 until clkNum ){
+      val j = clkNum - i -1
+      when( flitReg(j) ^ flitReg(j+1) ){
+        arbLock := "b1".U(clkNum.W) << j
+        isLock := true.B
+      }
+    }
+  } .elsewhen( clearCnt === 10.U ){
+    isLock := false.B
+  }
+
 
   val asyncSerDat = 
     Mux1H(
       (for { i <- 0 until clkNum } yield {
-        (arbLock === (1.U << i)) -> flitReg(i)
+        (arbLock === (1.U << i)) -> flitReg(i+(clkNum/2))
       })
     )
 
-  syncSerDat := ShiftRegister( asyncSerDat, 2 )
+
+  syncSerDat := asyncSerDat
 
 }
 
@@ -245,7 +237,9 @@ trait CDRInAxis{ this: CDRInBase =>
 
 class CDRIn extends CDRInBase 
 with CDRInAxis
-with CDRInOverSample
+with CDRInOverSample{
+  require(false)
+}
 
 class MPCDRIn extends CDRInBase 
 with CDRInAxis