ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

文件结构调整

Browse Source
This commit is contained in:
Ruige Lee
2025-02-26 15:36:57 +08:00
parent 598982cc95
commit ea6ea66040
9 changed files with 7 additions and 233 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/test/scala/gcd/test.scala
View File

@@ -59,14 +59,14 @@ object testModule extends App {
// ))
val cfg = new BackCfg
// val cfg = new BackCfg
(new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
ChiselGeneratorAnnotation(() => {
val soc = LazyModule(new BackSys()(cfg))
soc.module
})
))
// (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
// ChiselGeneratorAnnotation(() => {
// val soc = LazyModule(new BackSys()(cfg))
// soc.module
// })
// ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(