文件结构调整

src/main/scala/backBoard/pico/SimpleSRAM.scala.bk

@@ -0,0 +1,42 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+
+class SimpleSRAM()(implicit p: Parameters) extends BackModule{
+  class SimpleSRAMIO extends Bundle{
+    val mem = Flipped(new Mem_Port_Bundle)
+  }
+
+  val io: SimpleSRAMIO = IO(new SimpleSRAMIO)
+
+  val mem = SyncReadMem(1024, UInt(32.W))
+
+
+  io.mem.rdata := DontCare
+
+  when( io.mem.valid & io.mem.wstrb.extract(0) ){
+    mem.write( io.mem.addr(11,2), io.mem.wdata )
+
+    assert( io.mem.wstrb.extract(1) & io.mem.wstrb.extract(2) & io.mem.wstrb.extract(3) )
+  }
+
+  io.mem.rdata := mem.read(io.mem.addr(11,2), true.B)
+
+  val isReadAck = RegInit(false.B)
+  when( io.mem.fire ){
+    isReadAck := false.B
+  } .elsewhen( io.mem.valid & io.mem.wstrb === 0.U ){
+    isReadAck := true.B
+  }
+
+  io.mem.ready := 
+    ( io.mem.wstrb =/= 0.U & true.B    ) |
+    ( io.mem.wstrb === 0.U & isReadAck )
+
+}