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smwdt超时后停止计数；一同处理wdt0超时后停止计数

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This commit is contained in:
Ruige Lee
2025-09-29 12:20:09 +08:00
parent e4a0c8d30d
commit e86e7797e5
1 changed files with 5 additions and 4 deletions
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9
src/main/scala/backBoard/shin/MstSlvSwitch.scala
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@@ -454,13 +454,13 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) } val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) }
for( i <- 0 until 8 ){ for( i <- 0 until 8 ){
when( smUnit(i).io.enq ){ when( smUnit(i).io.enq || interface.io.wdtTrigger(2*i+1) ){
isWdtSMEnable(2*i) := false.B isWdtSMEnable(2*i) := false.B
} .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(2*i+1) ){ } .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(2*i+1) ){
isWdtSMEnable(2*i) := true.B isWdtSMEnable(2*i) := true.B
} }
when( smUnit(i).io.deq ){ when( smUnit(i).io.deq || interface.io.wdtTrigger(2*i+2) ){
isWdtSMEnable(2*i + 1) := false.B isWdtSMEnable(2*i + 1) := false.B
} .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(2*i+2) ){ } .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(2*i+2) ){
isWdtSMEnable(2*i + 1) := true.B isWdtSMEnable(2*i + 1) := true.B
@@ -484,8 +484,9 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
val wdtRec2RtnCnt = RegInit(0.U(32.W)) val wdtRec2RtnCnt = RegInit(0.U(32.W))
when( when(
(upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) | (upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) ||
~interface.io.cReg.wdtEnable.extract(0) ~interface.io.cReg.wdtEnable.extract(0) ||
interface.io.wdtTrigger(0)
){ ){
isWdtRec2RtnEnable := false.B isWdtRec2RtnEnable := false.B
} .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){