From e86e7797e548d85902e633b8cf948178f5536e08 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 29 Sep 2025 12:20:09 +0800 Subject: [PATCH] =?UTF-8?q?smwdt=E8=B6=85=E6=97=B6=E5=90=8E=E5=81=9C?= =?UTF-8?q?=E6=AD=A2=E8=AE=A1=E6=95=B0=EF=BC=9B=E4=B8=80=E5=90=8C=E5=A4=84?= =?UTF-8?q?=E7=90=86wdt0=E8=B6=85=E6=97=B6=E5=90=8E=E5=81=9C=E6=AD=A2?= =?UTF-8?q?=E8=AE=A1=E6=95=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/MstSlvSwitch.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 017c350..3a2124c 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -454,13 +454,13 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase => val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) } for( i <- 0 until 8 ){ - when( smUnit(i).io.enq ){ + when( smUnit(i).io.enq || interface.io.wdtTrigger(2*i+1) ){ isWdtSMEnable(2*i) := false.B } .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(2*i+1) ){ isWdtSMEnable(2*i) := true.B } - when( smUnit(i).io.deq ){ + when( smUnit(i).io.deq || interface.io.wdtTrigger(2*i+2) ){ isWdtSMEnable(2*i + 1) := false.B } .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(2*i+2) ){ isWdtSMEnable(2*i + 1) := true.B @@ -484,8 +484,9 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase => val wdtRec2RtnCnt = RegInit(0.U(32.W)) when( - (upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) | - ~interface.io.cReg.wdtEnable.extract(0) + (upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) || + ~interface.io.cReg.wdtEnable.extract(0) || + interface.io.wdtTrigger(0) ){ isWdtRec2RtnEnable := false.B } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){