diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
index 017c350..3a2124c 100644
--- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala
+++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
@@ -454,13 +454,13 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
   val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) }
 
   for( i <- 0 until 8 ){
-    when( smUnit(i).io.enq ){
+    when( smUnit(i).io.enq || interface.io.wdtTrigger(2*i+1) ){
       isWdtSMEnable(2*i) := false.B
     } .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(2*i+1) ){
       isWdtSMEnable(2*i) := true.B
     }
 
-    when( smUnit(i).io.deq  ){ 
+    when( smUnit(i).io.deq || interface.io.wdtTrigger(2*i+2)  ){ 
       isWdtSMEnable(2*i + 1) := false.B
     } .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(2*i+2) ){
       isWdtSMEnable(2*i + 1) := true.B
@@ -484,8 +484,9 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
   val wdtRec2RtnCnt = RegInit(0.U(32.W))
 
   when( 
-    (upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) |
-    ~interface.io.cReg.wdtEnable.extract(0)
+    (upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) ||
+    ~interface.io.cReg.wdtEnable.extract(0) ||
+    interface.io.wdtTrigger(0)
   ){
     isWdtRec2RtnEnable := false.B
   } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){