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FSMC直达sram

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RuigeLee
2024-03-21 10:43:57 +08:00
parent a5eba8edcf
commit e53687e11d
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/backBoard/BackBoardMst.scala
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@@ -118,11 +118,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
mirrorDown.io.enw := isAccessSRAM & fsmcCSSync(0) & fsmcWRSync(0) mirrorDown.io.enw := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn //isAccessSRAM & fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0)
mirrorDown.io.addrw := activeAddr mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := io.FSMC.ADIn mirrorDown.io.dataw := io.FSMC.ADIn
mirrorUp.io.enr := isAccessSRAM & fsmcCSSync(0) & fsmcRDSync(0) mirrorUp.io.enr := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn//isAccessSRAM & fsmcCSSync(0) & ~fsmcRDSync(1) & fsmcRDSync(0)
mirrorUp.io.addrr := activeAddr mirrorUp.io.addrr := activeAddr
io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar) io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)