diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 627774e..d79da79 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -118,11 +118,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
 
 
-    mirrorDown.io.enw    := isAccessSRAM & fsmcCSSync(0) & fsmcWRSync(0)
+    mirrorDown.io.enw    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn //isAccessSRAM & fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0)
     mirrorDown.io.addrw  := activeAddr
     mirrorDown.io.dataw  := io.FSMC.ADIn
 
-    mirrorUp.io.enr    := isAccessSRAM & fsmcCSSync(0) & fsmcRDSync(0)
+    mirrorUp.io.enr    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn//isAccessSRAM & fsmcCSSync(0) & ~fsmcRDSync(1) & fsmcRDSync(0)
     mirrorUp.io.addrr  := activeAddr
 
     io.FSMC.ADOut   := Mux( isAccessReg, regOut, mirrorUp.io.datar)