From e53687e11d741f85ab21f3af2853291446b6f934 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 21 Mar 2024 10:43:57 +0800 Subject: [PATCH] =?UTF-8?q?FSMC=E7=9B=B4=E8=BE=BEsram?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/BackBoardMst.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index 627774e..d79da79 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -118,11 +118,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase => - mirrorDown.io.enw := isAccessSRAM & fsmcCSSync(0) & fsmcWRSync(0) + mirrorDown.io.enw := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn //isAccessSRAM & fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) mirrorDown.io.addrw := activeAddr mirrorDown.io.dataw := io.FSMC.ADIn - mirrorUp.io.enr := isAccessSRAM & fsmcCSSync(0) & fsmcRDSync(0) + mirrorUp.io.enr := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn//isAccessSRAM & fsmcCSSync(0) & ~fsmcRDSync(1) & fsmcRDSync(0) mirrorUp.io.addrr := activeAddr io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)