修改dataw_async的更新策略
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@@ -128,12 +128,12 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
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}
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}
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}
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}
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when( bitSel === 0.U ){
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when( bitSel.andR ){
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when( byteSel > 3.U & isSpiWrite ){
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when( byteSel >= 4.U & isSpiWrite ){
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when( ~isPing_async ){
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when( ~isPing_async ){
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dataw_async(0) := exRegi
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dataw_async(0) := Cat( exRegi(3,0), qspi.mosi )
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} .otherwise{
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} .otherwise{
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dataw_async(1) := exRegi
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dataw_async(1) := Cat( exRegi(3,0), qspi.mosi )
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}
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}
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}
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}
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}
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}
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