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时序优化，计数从1开始计，从而避免一个减法器

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提前获取接收包长，提升最高频率
This commit is contained in:
RuigeLee
2024-10-22 16:11:30 +08:00
parent 55d1e6e8e7
commit e0ca51875e
1 changed files with 5 additions and 5 deletions
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10
src/main/scala/backBoard/shin/ShinMst.scala
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@@ -179,7 +179,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
val recvCnt = Reg(UInt(10.W)) val recvCnt = Reg(UInt(10.W))
val recvLength = recvHeader.asTypeOf(new Header_Info_Bundle).length val recvLength = RegEnable(recvHeader(15,4), upPendBuf.io.deq.fire & ( recvStateCurr === RecvStateHead ) & recvCnt === 3.U)
val isRecvEnd: Bool val isRecvEnd: Bool
isRecvEnd := recvStateCurr === RecvStateDeArm isRecvEnd := recvStateCurr === RecvStateDeArm
@@ -189,15 +189,15 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
recvStateNext := Mux1H(Seq( recvStateNext := Mux1H(Seq(
(recvStateCurr === RecvStateIdle) -> Mux( isSendTrig, RecvStateArm, RecvStateIdle ), //IDLE (recvStateCurr === RecvStateIdle) -> Mux( isSendTrig, RecvStateArm, RecvStateIdle ), //IDLE
(recvStateCurr === RecvStateArm) -> Mux( upPendBuf.io.deq.valid, RecvStateHead, RecvStateArm ), //Arm (recvStateCurr === RecvStateArm) -> Mux( upPendBuf.io.deq.valid, RecvStateHead, RecvStateArm ), //Arm
(recvStateCurr === RecvStateHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (headByte-1).U, RecvStatePayLoad, RecvStateHead ), RecvStateDeArm ), RecvStateHead ), //Header (recvStateCurr === RecvStateHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (headByte).U, RecvStatePayLoad, RecvStateHead ), RecvStateDeArm ), RecvStateHead ), //Header
(recvStateCurr === RecvStatePayLoad) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (recvLength-1.U), RecvStateCRC, RecvStatePayLoad ), RecvStateDeArm ), RecvStatePayLoad ), //payload (recvStateCurr === RecvStatePayLoad) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (recvLength), RecvStateCRC, RecvStatePayLoad ), RecvStateDeArm ), RecvStatePayLoad ), //payload
(recvStateCurr === RecvStateCRC) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, RecvStateDeArm, RecvStateCRC ),//crc (recvStateCurr === RecvStateCRC) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, RecvStateDeArm, RecvStateCRC ),//crc
(recvStateCurr === RecvStateDeArm) -> RecvStateIdle,//de-arm (recvStateCurr === RecvStateDeArm) -> RecvStateIdle,//de-arm
)) ))
when( recvStateCurr =/= recvStateNext ){ when( recvStateCurr =/= recvStateNext ){
recvCnt := 0.U recvCnt := 1.U
} .elsewhen( upPendBuf.io.deq.fire ){ } .elsewhen( upPendBuf.io.deq.fire ){
recvCnt := recvCnt + 1.U recvCnt := recvCnt + 1.U
} }
@@ -223,7 +223,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
} .elsewhen( recvStateCurr === RecvStatePayLoad & recvStateNext === RecvStateDeArm ){ } .elsewhen( recvStateCurr === RecvStatePayLoad & recvStateNext === RecvStateDeArm ){
isRecvError := true.B isRecvError := true.B
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n") printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
} .elsewhen( recvStateCurr === RecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & recvCnt =/= 3.U ){ } .elsewhen( recvStateCurr === RecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & recvCnt =/= 4.U ){
isRecvError := true.B isRecvError := true.B
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n") printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
} }