From e0ca51875e0af0b92c2e19533f915cded5e9a3ec Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 22 Oct 2024 16:11:30 +0800 Subject: [PATCH] =?UTF-8?q?=E6=97=B6=E5=BA=8F=E4=BC=98=E5=8C=96=EF=BC=8C?= =?UTF-8?q?=E8=AE=A1=E6=95=B0=E4=BB=8E1=E5=BC=80=E5=A7=8B=E8=AE=A1?= =?UTF-8?q?=EF=BC=8C=E4=BB=8E=E8=80=8C=E9=81=BF=E5=85=8D=E4=B8=80=E4=B8=AA?= =?UTF-8?q?=E5=87=8F=E6=B3=95=E5=99=A8=20=E6=8F=90=E5=89=8D=E8=8E=B7?= =?UTF-8?q?=E5=8F=96=E6=8E=A5=E6=94=B6=E5=8C=85=E9=95=BF=EF=BC=8C=E6=8F=90?= =?UTF-8?q?=E5=8D=87=E6=9C=80=E9=AB=98=E9=A2=91=E7=8E=87?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/ShinMst.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/backBoard/shin/ShinMst.scala b/src/main/scala/backBoard/shin/ShinMst.scala index 4147db8..cf97a37 100644 --- a/src/main/scala/backBoard/shin/ShinMst.scala +++ b/src/main/scala/backBoard/shin/ShinMst.scala @@ -179,7 +179,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase => val recvCnt = Reg(UInt(10.W)) - val recvLength = recvHeader.asTypeOf(new Header_Info_Bundle).length + val recvLength = RegEnable(recvHeader(15,4), upPendBuf.io.deq.fire & ( recvStateCurr === RecvStateHead ) & recvCnt === 3.U) val isRecvEnd: Bool isRecvEnd := recvStateCurr === RecvStateDeArm @@ -189,15 +189,15 @@ trait ShinMstRecv{ this: ShinMstPhyBase => recvStateNext := Mux1H(Seq( (recvStateCurr === RecvStateIdle) -> Mux( isSendTrig, RecvStateArm, RecvStateIdle ), //IDLE (recvStateCurr === RecvStateArm) -> Mux( upPendBuf.io.deq.valid, RecvStateHead, RecvStateArm ), //Arm - (recvStateCurr === RecvStateHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (headByte-1).U, RecvStatePayLoad, RecvStateHead ), RecvStateDeArm ), RecvStateHead ), //Header - (recvStateCurr === RecvStatePayLoad) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (recvLength-1.U), RecvStateCRC, RecvStatePayLoad ), RecvStateDeArm ), RecvStatePayLoad ), //payload + (recvStateCurr === RecvStateHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (headByte).U, RecvStatePayLoad, RecvStateHead ), RecvStateDeArm ), RecvStateHead ), //Header + (recvStateCurr === RecvStatePayLoad) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (recvLength), RecvStateCRC, RecvStatePayLoad ), RecvStateDeArm ), RecvStatePayLoad ), //payload (recvStateCurr === RecvStateCRC) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, RecvStateDeArm, RecvStateCRC ),//crc (recvStateCurr === RecvStateDeArm) -> RecvStateIdle,//de-arm )) when( recvStateCurr =/= recvStateNext ){ - recvCnt := 0.U + recvCnt := 1.U } .elsewhen( upPendBuf.io.deq.fire ){ recvCnt := recvCnt + 1.U } @@ -223,7 +223,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase => } .elsewhen( recvStateCurr === RecvStatePayLoad & recvStateNext === RecvStateDeArm ){ isRecvError := true.B printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n") - } .elsewhen( recvStateCurr === RecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & recvCnt =/= 3.U ){ + } .elsewhen( recvStateCurr === RecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & recvCnt =/= 4.U ){ isRecvError := true.B printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n") }