diff --git a/src/main/scala/backBoard/shin/ShinMst.scala b/src/main/scala/backBoard/shin/ShinMst.scala
index 4147db8..cf97a37 100644
--- a/src/main/scala/backBoard/shin/ShinMst.scala
+++ b/src/main/scala/backBoard/shin/ShinMst.scala
@@ -179,7 +179,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
 
   val recvCnt = Reg(UInt(10.W))
 
-  val recvLength = recvHeader.asTypeOf(new Header_Info_Bundle).length
+  val recvLength = RegEnable(recvHeader(15,4), upPendBuf.io.deq.fire & ( recvStateCurr === RecvStateHead ) & recvCnt === 3.U)
 
   val isRecvEnd: Bool
   isRecvEnd := recvStateCurr === RecvStateDeArm
@@ -189,15 +189,15 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
   recvStateNext := Mux1H(Seq(
     (recvStateCurr === RecvStateIdle)    -> Mux( isSendTrig, RecvStateArm, RecvStateIdle ), //IDLE
     (recvStateCurr === RecvStateArm)     -> Mux( upPendBuf.io.deq.valid, RecvStateHead, RecvStateArm ), //Arm
-    (recvStateCurr === RecvStateHead)    -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (headByte-1).U, RecvStatePayLoad, RecvStateHead ), RecvStateDeArm ), RecvStateHead ), //Header
-    (recvStateCurr === RecvStatePayLoad) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (recvLength-1.U), RecvStateCRC, RecvStatePayLoad ), RecvStateDeArm ), RecvStatePayLoad ), //payload
+    (recvStateCurr === RecvStateHead)    -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (headByte).U, RecvStatePayLoad, RecvStateHead ), RecvStateDeArm ), RecvStateHead ), //Header
+    (recvStateCurr === RecvStatePayLoad) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (recvLength), RecvStateCRC, RecvStatePayLoad ), RecvStateDeArm ), RecvStatePayLoad ), //payload
     (recvStateCurr === RecvStateCRC)     -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, RecvStateDeArm, RecvStateCRC ),//crc
     (recvStateCurr === RecvStateDeArm)   -> RecvStateIdle,//de-arm
 
   ))
 
   when( recvStateCurr =/= recvStateNext ){
-    recvCnt := 0.U
+    recvCnt := 1.U
   } .elsewhen( upPendBuf.io.deq.fire ){
     recvCnt := recvCnt + 1.U
   }
@@ -223,7 +223,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
   } .elsewhen( recvStateCurr === RecvStatePayLoad & recvStateNext === RecvStateDeArm ){
     isRecvError := true.B
     printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
-  } .elsewhen( recvStateCurr === RecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & recvCnt =/= 3.U ){
+  } .elsewhen( recvStateCurr === RecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & recvCnt =/= 4.U ){
     isRecvError := true.B
     printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
   }