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This commit is contained in:
Ruige Lee
2025-05-16 20:17:49 +08:00
parent a0deb68fd6
commit df4f4f445b
1 changed files with 5 additions and 5 deletions
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10
src/main/scala/backBoard/shin/Interface.scala
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@@ -248,10 +248,10 @@ abstract class InterfaceBase extends Module{
(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ), (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
(addr === "h21".U & isMstMode) -> mReg.txLength, (addr === "h21".U & isMstMode) -> mReg.txLength,
(addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(7,0), (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
(addr === "h26".U & isMstMode) -> mReg.rplTimeStampTx(15,8), (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
@@ -458,8 +458,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
mReg.rplTimeStampTx := mReg.rplTimeStampTx :=
Cat( Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === "h26".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U ),
RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U ) RegEnable( dataw, 0.U, isEnW & addrSel === "h24".U )
) )