From df4f4f445b4e85feb2623e1249922de9bda13e82 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 16 May 2025 20:17:49 +0800 Subject: [PATCH] =?UTF-8?q?=E5=90=8C=E4=B8=8A?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 7c3f613..21144bf 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -248,10 +248,10 @@ abstract class InterfaceBase extends Module{ (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ), - (addr === "h21".U & isMstMode) -> mReg.txLength, + (addr === "h21".U & isMstMode) -> mReg.txLength, - (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(7,0), - (addr === "h26".U & isMstMode) -> mReg.rplTimeStampTx(15,8), + (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0), + (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8), @@ -458,8 +458,8 @@ trait InterfaceMCUop{ this: InterfaceBase => mReg.rplTimeStampTx := Cat( - RegEnable( dataw, 0.U, isEnW & addrSel === "h26".U ), - RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U ) + RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U ), + RegEnable( dataw, 0.U, isEnW & addrSel === "h24".U ) )