diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 7c3f613..21144bf 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -248,10 +248,10 @@ abstract class InterfaceBase extends Module{
 
 
         (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
-        (addr === "h21".U & isMstMode) -> mReg.txLength,
+                (addr === "h21".U & isMstMode) -> mReg.txLength,
 
-        (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
-        (addr === "h26".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
+        (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
+        (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
 
 
 
@@ -458,8 +458,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
   mReg.rplTimeStampTx := 
     Cat(
-      RegEnable( dataw, 0.U, isEnW & addrSel === "h26".U ),
-      RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U )
+      RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U ),
+      RegEnable( dataw, 0.U, isEnW & addrSel === "h24".U )
     )