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优化core的tl接口，两拍握手，指令速度从5拍一条指令变为4拍一条指令

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RuigeLee
2024-10-28 10:37:08 +08:00
parent 78d54d2083
commit d8361401b5
1 changed files with 12 additions and 12 deletions
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24
src/main/scala/backBoard/pico/Picorv32_tl.scala
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@@ -34,27 +34,27 @@ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule{
core.io.irq := io.irq
io.eoi := core.io.eoi
val tlStateNext = Wire( UInt(2.W) )
val tlStateCurr = RegNext(tlStateNext, 0.U)
// val tlStateNext = Wire( UInt(2.W) )
// val tlStateCurr = RegNext(tlStateNext, 0.U)
tlStateNext := Mux1H(Seq(
(tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE
(tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE
(tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE
))
// tlStateNext := Mux1H(Seq(
// (tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE
// (tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE
// (tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE
// ))
val tlaValid = RegInit(false.B)
val isTlaValidAck = RegInit(true.B)
when( io.tla.fire ){
tlaValid := false.B
} .elsewhen( tlStateCurr === 0.U & tlStateNext === 1.U ){
tlaValid := true.B
isTlaValidAck := false.B
} .elsewhen( io.tld.fire ){
isTlaValidAck := true.B
}
core.io.mem_ready := io.tld.fire
core.io.mem_rdata := io.tld.bits.data
io.tld.ready := true.B
io.tla.valid := tlaValid
io.tla.valid := isTlaValidAck & core.io.mem_valid
when( core.io.mem_wstrb.orR ){
io.tla.bits :=