diff --git a/src/main/scala/backBoard/pico/Picorv32_tl.scala b/src/main/scala/backBoard/pico/Picorv32_tl.scala
index af2e4e7..3fbeba1 100644
--- a/src/main/scala/backBoard/pico/Picorv32_tl.scala
+++ b/src/main/scala/backBoard/pico/Picorv32_tl.scala
@@ -34,27 +34,27 @@ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule{
 	core.io.irq := io.irq
 	io.eoi := core.io.eoi
 
-  val tlStateNext = Wire( UInt(2.W) )
-  val tlStateCurr = RegNext(tlStateNext, 0.U)
+  // val tlStateNext = Wire( UInt(2.W) )
+  // val tlStateCurr = RegNext(tlStateNext, 0.U)
 
-  tlStateNext := Mux1H(Seq(
-    (tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE
-    (tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE
-    (tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE
-  ))
+  // tlStateNext := Mux1H(Seq(
+  //   (tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE
+  //   (tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE
+  //   (tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE
+  // ))
 
-  val tlaValid = RegInit(false.B)
+  val isTlaValidAck = RegInit(true.B)
 
   when( io.tla.fire ){
-    tlaValid := false.B
-  } .elsewhen( tlStateCurr === 0.U & tlStateNext === 1.U ){
-    tlaValid := true.B
+    isTlaValidAck := false.B
+  } .elsewhen( io.tld.fire ){
+    isTlaValidAck := true.B
   }
 
   core.io.mem_ready := io.tld.fire
   core.io.mem_rdata := io.tld.bits.data
   io.tld.ready := true.B
-  io.tla.valid := tlaValid
+  io.tla.valid := isTlaValidAck & core.io.mem_valid
 
   when( core.io.mem_wstrb.orR ){
     io.tla.bits :=