From d8361401b58ea741cd9a9dda79b997fb3fcf6939 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Mon, 28 Oct 2024 10:37:08 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BC=98=E5=8C=96core=E7=9A=84tl=E6=8E=A5?= =?UTF-8?q?=E5=8F=A3=EF=BC=8C=E4=B8=A4=E6=8B=8D=E6=8F=A1=E6=89=8B=EF=BC=8C?= =?UTF-8?q?=E6=8C=87=E4=BB=A4=E9=80=9F=E5=BA=A6=E4=BB=8E5=E6=8B=8D?= =?UTF-8?q?=E4=B8=80=E6=9D=A1=E6=8C=87=E4=BB=A4=E5=8F=98=E4=B8=BA4?= =?UTF-8?q?=E6=8B=8D=E4=B8=80=E6=9D=A1=E6=8C=87=E4=BB=A4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/pico/Picorv32_tl.scala | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/main/scala/backBoard/pico/Picorv32_tl.scala b/src/main/scala/backBoard/pico/Picorv32_tl.scala index af2e4e7..3fbeba1 100644 --- a/src/main/scala/backBoard/pico/Picorv32_tl.scala +++ b/src/main/scala/backBoard/pico/Picorv32_tl.scala @@ -34,27 +34,27 @@ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule{ core.io.irq := io.irq io.eoi := core.io.eoi - val tlStateNext = Wire( UInt(2.W) ) - val tlStateCurr = RegNext(tlStateNext, 0.U) + // val tlStateNext = Wire( UInt(2.W) ) + // val tlStateCurr = RegNext(tlStateNext, 0.U) - tlStateNext := Mux1H(Seq( - (tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE - (tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE - (tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE - )) + // tlStateNext := Mux1H(Seq( + // (tlStateCurr === 0.U) -> Mux( core.io.mem_valid, 1.U, 0.U ), //IDLE + // (tlStateCurr === 1.U) -> Mux( io.tla.fire, 2.U, 1.U ), //A FIRE + // (tlStateCurr === 2.U) -> Mux( io.tld.fire, 0.U, 2.U ), //D FIRE + // )) - val tlaValid = RegInit(false.B) + val isTlaValidAck = RegInit(true.B) when( io.tla.fire ){ - tlaValid := false.B - } .elsewhen( tlStateCurr === 0.U & tlStateNext === 1.U ){ - tlaValid := true.B + isTlaValidAck := false.B + } .elsewhen( io.tld.fire ){ + isTlaValidAck := true.B } core.io.mem_ready := io.tld.fire core.io.mem_rdata := io.tld.bits.data io.tld.ready := true.B - io.tla.valid := tlaValid + io.tla.valid := isTlaValidAck & core.io.mem_valid when( core.io.mem_wstrb.orR ){ io.tla.bits :=