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从机掉线处理

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RuigeLee
2024-04-17 19:09:25 +08:00
parent 98ca3b1ab1
commit d831cc2659
1 changed files with 36 additions and 12 deletions
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44
src/main/scala/backBoard/BackBoardMst.scala
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@@ -517,30 +517,54 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
when( lvdsMst.io.closed_loop_err ){
val shiftClosedLoopErr = ShiftRegisters( lvdsMst.io.closed_loop_err | lvdsMst.io.upstream_cdr_err, 6, false.B, true.B )
when( ~shiftClosedLoopErr(0) & lvdsMst.io.closed_loop_err ){
//slvOffLine := lvdsMst.io.link_err_location(5,0)
mirrorReg.io.addrB := 3.U
mirrorReg.io.datawB := lvdsMst.io.link_err_location(5,0)
mirrorReg.io.enwB := true.B
} .elsewhen( RegNext(lvdsMst.io.closed_loop_err, false.B)){
} .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){
//statusLinkErr := true.B
mirrorReg.io.addrB := 10.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
} .elsewhen( ~shiftClosedLoopErr(2) & shiftClosedLoopErr(1) ){
mirrorReg.io.addrB := 8.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
ctrlSynch := false.B
} .elsewhen( ~shiftClosedLoopErr(3) & shiftClosedLoopErr(2) ){
mirrorReg.io.addrB := 9.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
ctrlTransmit := false.B
} .elsewhen( ~shiftClosedLoopErr(4) & shiftClosedLoopErr(3) ){
mirrorReg.io.addrB := 13.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
ctrlUnicast := false.B
} .elsewhen( ~shiftClosedLoopErr(5) & shiftClosedLoopErr(4) ){
interrupt := true.B
}
when( lvdsMst.io.upstream_cdr_err ){
// statusCDRErr := true.B
mirrorReg.io.addrB := 11.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
interrupt := true.B
}
// when( lvdsMst.io.upstream_cdr_err ){
// // statusCDRErr := true.B
// mirrorReg.io.addrB := 11.U
// mirrorReg.io.datawB := 1.U
// mirrorReg.io.enwB := true.B
// interrupt := true.B
// }
when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
// statusCRCErr := true.B