611 lines
14 KiB
Scala
611 lines
14 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class FSMC_Port_Bundle extends Bundle{
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val ADIn = Input(UInt(16.W))
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val ADOut = Output(UInt(16.W))
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val ADOEn = Output(Bool())
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val csn = Input(Bool())
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val rdn = Input(Bool())
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val wrn = Input(Bool())
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val advn = Input(Bool())
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}
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class BackBoardMstIO extends Bundle{
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val FSMC = new FSMC_Port_Bundle
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val reset_calib = Input(Bool())
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val oser_pclk = Input(Bool()) //10M
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val oser_fclk = Input(Bool()) //50M
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val ides_pclk = Input(Bool()) //100M
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val ides_fclk = Input(Bool()) //400M
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val lvds_down_dout = Output(Bool())
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val lvds_up_din = Input(Bool())
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val interrupt = Output(Bool())
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val testIO = Input(Bool())
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}
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class BackBoardMstBase extends Module{ //10M
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val io: BackBoardMstIO = IO(new BackBoardMstIO)
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val lvdsMst = Module(new Lvds_Bus_Master)
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val mirrorDown = Module(new MirrorSRAMDown())
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val mirrorUp = Module(new MirrorSRAMUp())
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val mirrorReg = Module(new MirrorSRAMDP())
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mirrorReg.io.addrB := DontCare
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mirrorReg.io.datawB := DontCare
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mirrorReg.io.enwB := false.B
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mirrorReg.io.enrB := false.B
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assert( ~(mirrorReg.io.enwA & mirrorReg.io.enrA) )
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assert( ~(mirrorReg.io.enwB & mirrorReg.io.enrB) )
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val ctrlTransmit = RegInit( false.B )
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val ctrlUnicast = RegInit( false.B )
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val ctrlSynch = RegInit( false.B )
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val ctrlInit = RegInit( false.B )
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val slvNum = RegInit(0.U(6.W))
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val interrupt = RegInit(false.B); io.interrupt := interrupt
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val slaveDataLength = Reg(UInt(8.W)) //(8/8)*32-1
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lvdsMst.io.rst_n := ~reset.asBool
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lvdsMst.io.reset_calib := io.reset_calib
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lvdsMst.io.oser_pclk := io.oser_pclk
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lvdsMst.io.oser_fclk := io.oser_fclk
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lvdsMst.io.ides_pclk := io.ides_pclk
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lvdsMst.io.ides_fclk := io.ides_fclk
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io.lvds_down_dout := lvdsMst.io.lvds_down_dout
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lvdsMst.io.lvds_up_din := io.lvds_up_din
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mirrorDown.io.clockr := io.oser_pclk.asBool
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mirrorDown.io.clockw := io.ides_pclk.asBool //100M
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mirrorUp.io.clockw := io.oser_pclk.asBool
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mirrorUp.io.clockr := io.ides_pclk.asBool //100M
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mirrorReg.io.clockA := io.ides_pclk.asBool //100M
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mirrorReg.io.clockB := io.oser_pclk.asBool //10M
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when(interrupt === true.B){
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interrupt := false.B
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}
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}
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trait BackBoardMstFSMC{ this: BackBoardMstBase =>
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withClockAndReset( io.ides_pclk.asClock, reset ){//100M
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io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn
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val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)
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val isAccessSRAM = ~latchAddr.extract(10)
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val isAccessReg = latchAddr.extract(10)
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val activeAddr = latchAddr(9,0)
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mirrorDown.io.enw := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn
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mirrorDown.io.addrw := activeAddr
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mirrorDown.io.dataw := io.FSMC.ADIn
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mirrorUp.io.enr := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn
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mirrorUp.io.addrr := activeAddr
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mirrorReg.io.addrA := activeAddr
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mirrorReg.io.datawA := io.FSMC.ADIn
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mirrorReg.io.enwA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
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mirrorReg.io.enrA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn
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io.FSMC.ADOut := Mux( isAccessReg, mirrorReg.io.datarA, mirrorUp.io.datar)
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}
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//10M
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val testIOShift = ShiftRegisters(io.testIO, 3, false.B, true.B)
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when(~testIOShift(0) & io.testIO){
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mirrorReg.io.addrB := 1.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( ~testIOShift(1) & testIOShift(0)){
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when( mirrorReg.io.datarB === 0.U ){
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ctrlInit := true.B
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}
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when( mirrorReg.io.datarB === 1.U ){
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ctrlSynch := true.B
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}
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when( mirrorReg.io.datarB === 5.U ){
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ctrlTransmit := true.B
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}
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when( mirrorReg.io.datarB === 6.U ){
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ctrlUnicast := true.B
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}
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}
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}
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abstract class BackBoardMstLVDSBase extends BackBoardMstBase
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with BackBoardMstFSMC
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{
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val frame_info_update_en = RegInit(false.B)
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val slave_type_num = RegInit(0.U(8.W))
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val tx_start = RegInit(false.B)
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lvdsMst.io.frame_info_update_en := frame_info_update_en
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lvdsMst.io.slave_type_num := slave_type_num
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lvdsMst.io.slave_data_length := slaveDataLength
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lvdsMst.io.tx_start := tx_start
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val stateCur = RegInit(15.U(4.W))
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}
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trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
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val isInitStart = ~RegNext(ctrlInit, false.B) & ctrlInit
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val timeoutCnt = Reg(UInt(13.W))
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when(ctrlInit){
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when( isInitStart ){
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stateCur := 0.U
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frame_info_update_en := false.B
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slave_type_num := 0.U
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tx_start := false.B
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} .elsewhen( stateCur === 0.U ){
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stateCur := 1.U
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// write statusInit
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mirrorReg.io.addrB := 7.U
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mirrorReg.io.datawB := 0.U
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mirrorReg.io.enwB := true.B
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} .elsewhen( stateCur === 1.U ){
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stateCur := 2.U
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//req slvnum
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mirrorReg.io.addrB := 2.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( stateCur === 2.U ){
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stateCur := 3.U
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//lock slvNum
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slvNum := mirrorReg.io.datarB
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//req slaveDataLength
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mirrorReg.io.addrB := 6.U
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mirrorReg.io.enrB := true.B
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}
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.elsewhen( stateCur === 3.U ){
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stateCur := 4.U
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//lock slaveDataLength
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slaveDataLength := mirrorReg.io.datarB
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frame_info_update_en := true.B
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slave_type_num := Cat( "b00".U(2.W), slvNum )
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// slaveDataLength := slaveDataLength
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tx_start := false.B
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} .elsewhen( stateCur === 4.U ){ // tx start
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stateCur := 5.U
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timeoutCnt := 0.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 5.U ){
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tx_start := false.B
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timeoutCnt := timeoutCnt + 1.U
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when( lvdsMst.io.slave_link_num_valid ){
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stateCur := 6.U
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//linkNum
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mirrorReg.io.addrB := 5.U
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mirrorReg.io.datawB := lvdsMst.io.slave_link_num
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mirrorReg.io.enwB := true.B
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}
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when( timeoutCnt === 6000.U ){
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stateCur := 6.U
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//linkNum
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mirrorReg.io.addrB := 5.U
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mirrorReg.io.datawB := 0.U
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mirrorReg.io.enwB := true.B
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}
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} .elsewhen( stateCur === 6.U ){
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stateCur := 7.U
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//statusInit
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mirrorReg.io.addrB := 7.U
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mirrorReg.io.datawB := 1.U
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mirrorReg.io.enwB := true.B
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ctrlInit := false.B
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interrupt := true.B
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} .elsewhen( stateCur === 7.U ){
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}
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}
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}
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trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
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val isSyncStart = ~RegNext( ctrlSynch, false.B) & ctrlSynch
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when( ctrlSynch ){
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when( isSyncStart ){
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stateCur := 0.U
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frame_info_update_en := false.B
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slave_type_num := 0.U
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tx_start := false.B
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} .elsewhen( stateCur === 0.U ){ //statusSynch
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stateCur := 1.U
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mirrorReg.io.addrB := 8.U
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mirrorReg.io.datawB := 0.U
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mirrorReg.io.enwB := true.B
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} .elsewhen( stateCur === 1.U ){
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stateCur := 2.U
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//req slvnum
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mirrorReg.io.addrB := 2.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( stateCur === 2.U ){ //slaveDataLength
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stateCur := 3.U
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//lock slvNum
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slvNum := mirrorReg.io.datarB
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mirrorReg.io.addrB := 6.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( stateCur === 3.U ){
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stateCur := 4.U
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//lock slaveDataLength
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slaveDataLength := mirrorReg.io.datarB
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frame_info_update_en := true.B
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slave_type_num := Cat( "b01".U(2.W), slvNum )
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// slaveDataLength := slaveDataLength
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tx_start := false.B
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} .elsewhen( stateCur === 4.U ){ // tx start
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stateCur := 5.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 5.U ){
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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stateCur := 6.U
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//statusSync
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mirrorReg.io.addrB := 8.U
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mirrorReg.io.datawB := 1.U
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mirrorReg.io.enwB := true.B
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ctrlSynch := false.B
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interrupt := true.B
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}
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} .otherwise{
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}
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}
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}
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trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
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val isTransStart = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)
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when(ctrlTransmit){
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when( isTransStart ){ //reset
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stateCur := 0.U
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frame_info_update_en := false.B
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slave_type_num := 0.U
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tx_start := false.B
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} .elsewhen( stateCur === 0.U ){ //statusTransmit
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stateCur := 1.U
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mirrorReg.io.addrB := 9.U
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mirrorReg.io.datawB := 0.U
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mirrorReg.io.enwB := true.B
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} .elsewhen( stateCur === 1.U ){ //slvnum
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stateCur := 2.U
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mirrorReg.io.addrB := 2.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( stateCur === 2.U ){ //slaveDataLength
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stateCur := 3.U
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//lock slvNum
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slvNum := mirrorReg.io.datarB
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mirrorReg.io.addrB := 6.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( stateCur === 3.U ){ //setting
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stateCur := 4.U
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//lock slaveDataLength
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slaveDataLength := mirrorReg.io.datarB
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frame_info_update_en := true.B
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slave_type_num := Cat( "b10".U(2.W), slvNum )
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// slaveDataLength := slaveDataLength
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tx_start := false.B
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} .elsewhen( stateCur === 4.U ){ // tx start
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stateCur := 5.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 5.U ){ //waiting for busy drop
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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stateCur := 6.U
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}
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} .elsewhen( stateCur === 6.U ){
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when( lvdsMst.io.upstream_crc_valid ){
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stateCur := 7.U
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//statusTransmit
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mirrorReg.io.addrB := 9.U
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mirrorReg.io.datawB := 1.U
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mirrorReg.io.enwB := true.B
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ctrlTransmit := false.B
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interrupt := true.B
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}
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} .elsewhen( stateCur === 7.U ){
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// stateCur := 8.U
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} .otherwise{
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}
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}
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}
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trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
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val isUnicast = ctrlUnicast & ~RegNext(ctrlUnicast, false.B)
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when(ctrlUnicast){
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when( isUnicast ){ //reset
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stateCur := 0.U
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frame_info_update_en := false.B
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slave_type_num := 0.U
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tx_start := false.B
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} .elsewhen( stateCur === 0.U ){ //statusUnicast
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stateCur := 1.U
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mirrorReg.io.addrB := 13.U
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mirrorReg.io.datawB := 0.U
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mirrorReg.io.enwB := true.B
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} .elsewhen( stateCur === 1.U ){ //slvnum
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stateCur := 2.U
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mirrorReg.io.addrB := 2.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( stateCur === 2.U ){ //slaveDataLength
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stateCur := 3.U
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//lock slvNum
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slvNum := mirrorReg.io.datarB
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mirrorReg.io.addrB := 6.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( stateCur === 3.U ){ //setting
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stateCur := 4.U
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//lock slaveDataLength
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slaveDataLength := mirrorReg.io.datarB
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frame_info_update_en := true.B
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slave_type_num := Cat( "b11".U(2.W), slvNum )
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// slaveDataLength := slaveDataLength
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tx_start := false.B
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} .elsewhen( stateCur === 4.U ){ // tx start
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stateCur := 5.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 5.U ){ //waiting for busy drop
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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stateCur := 6.U
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}
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} .elsewhen( stateCur === 6.U ){
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when( lvdsMst.io.upstream_crc_valid ){
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stateCur := 7.U
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//statusUnicast
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mirrorReg.io.addrB := 13.U
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mirrorReg.io.datawB := 1.U
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mirrorReg.io.enwB := true.B
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ctrlUnicast := false.B
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interrupt := true.B
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}
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} .elsewhen( stateCur === 7.U ){
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// stateCur := 8.U
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} .otherwise{
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}
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}
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}
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trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
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val shiftClosedLoopErr = ShiftRegisters( lvdsMst.io.closed_loop_err | lvdsMst.io.upstream_cdr_err, 6, false.B, true.B )
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when( ~shiftClosedLoopErr(0) & lvdsMst.io.closed_loop_err ){
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//slvOffLine := lvdsMst.io.link_err_location(5,0)
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mirrorReg.io.addrB := 3.U
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mirrorReg.io.datawB := lvdsMst.io.link_err_location(5,0)
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mirrorReg.io.enwB := true.B
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} .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){
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//statusLinkErr := true.B
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mirrorReg.io.addrB := 10.U
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mirrorReg.io.datawB := 1.U
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mirrorReg.io.enwB := true.B
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} .elsewhen( ~shiftClosedLoopErr(2) & shiftClosedLoopErr(1) ){
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mirrorReg.io.addrB := 8.U
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mirrorReg.io.datawB := 1.U
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mirrorReg.io.enwB := true.B
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ctrlSynch := false.B
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} .elsewhen( ~shiftClosedLoopErr(3) & shiftClosedLoopErr(2) ){
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mirrorReg.io.addrB := 9.U
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mirrorReg.io.datawB := 1.U
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mirrorReg.io.enwB := true.B
|
|
|
|
ctrlTransmit := false.B
|
|
|
|
} .elsewhen( ~shiftClosedLoopErr(4) & shiftClosedLoopErr(3) ){
|
|
mirrorReg.io.addrB := 13.U
|
|
mirrorReg.io.datawB := 1.U
|
|
mirrorReg.io.enwB := true.B
|
|
|
|
ctrlUnicast := false.B
|
|
} .elsewhen( ~shiftClosedLoopErr(5) & shiftClosedLoopErr(4) ){
|
|
interrupt := true.B
|
|
}
|
|
|
|
|
|
|
|
|
|
// when( lvdsMst.io.upstream_cdr_err ){
|
|
// // statusCDRErr := true.B
|
|
// mirrorReg.io.addrB := 11.U
|
|
// mirrorReg.io.datawB := 1.U
|
|
// mirrorReg.io.enwB := true.B
|
|
// interrupt := true.B
|
|
// }
|
|
|
|
when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
|
|
// statusCRCErr := true.B
|
|
mirrorReg.io.addrB := 12.U
|
|
mirrorReg.io.datawB := 1.U
|
|
mirrorReg.io.enwB := true.B
|
|
interrupt := true.B
|
|
}
|
|
|
|
}
|
|
|
|
class BackBoardMst extends BackBoardMstLVDSBase
|
|
with BackBoardMstLVDSInit
|
|
with BackBoardMstLVDSSync
|
|
with BackBoardMstLVDSTransmit
|
|
with BackBoardMstLVDSUnicast
|
|
with BackBoardMstLVDSError{
|
|
|
|
val addrr = RegInit(0.U(11.W))
|
|
val addrw = RegInit(0.U(11.W))
|
|
|
|
when( isTransStart | isUnicast ){
|
|
addrw := 0.U
|
|
} .elsewhen( lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){
|
|
assert( (stateCur === 5.U) || (stateCur === 6.U) )
|
|
addrw := addrw + 1.U
|
|
}
|
|
|
|
when( isTransStart | isUnicast ){
|
|
addrr := 0.U
|
|
} .elsewhen( lvdsMst.io.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){
|
|
addrr := addrr + 1.U
|
|
}
|
|
|
|
mirrorDown.io.enr := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast)
|
|
lvdsMst.io.tx_data_in := mirrorDown.io.datar
|
|
mirrorDown.io.addrr := addrr
|
|
|
|
mirrorUp.io.enw := lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast)
|
|
mirrorUp.io.dataw := lvdsMst.io.rx_data_out
|
|
mirrorUp.io.addrw := addrw
|
|
|
|
}
|