diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index dd7edc1..c9b540c 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -517,31 +517,55 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
 
 
 trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
-  when( lvdsMst.io.closed_loop_err ){
+  val shiftClosedLoopErr = ShiftRegisters( lvdsMst.io.closed_loop_err | lvdsMst.io.upstream_cdr_err, 6, false.B, true.B )
+  when( ~shiftClosedLoopErr(0) & lvdsMst.io.closed_loop_err ){
 
     //slvOffLine    := lvdsMst.io.link_err_location(5,0)
     mirrorReg.io.addrB  := 3.U
     mirrorReg.io.datawB := lvdsMst.io.link_err_location(5,0)
-    mirrorReg.io.enwB   := true.B    
-
-  } .elsewhen( RegNext(lvdsMst.io.closed_loop_err, false.B)){
+    mirrorReg.io.enwB   := true.B
 
+  } .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){
     //statusLinkErr := true.B
     mirrorReg.io.addrB  := 10.U
     mirrorReg.io.datawB := 1.U
-    mirrorReg.io.enwB   := true.B   
+    mirrorReg.io.enwB   := true.B
 
-    interrupt     := true.B
-  }
-
-  when( lvdsMst.io.upstream_cdr_err ){
-    // statusCDRErr := true.B
-    mirrorReg.io.addrB  := 11.U
+  } .elsewhen( ~shiftClosedLoopErr(2) & shiftClosedLoopErr(1) ){
+    mirrorReg.io.addrB  := 8.U
     mirrorReg.io.datawB := 1.U
-    mirrorReg.io.enwB   := true.B   
+    mirrorReg.io.enwB   := true.B
+
+    ctrlSynch   := false.B
+
+  } .elsewhen( ~shiftClosedLoopErr(3) & shiftClosedLoopErr(2) ){
+    mirrorReg.io.addrB  := 9.U
+    mirrorReg.io.datawB := 1.U
+    mirrorReg.io.enwB   := true.B
+
+    ctrlTransmit := false.B
+
+  } .elsewhen( ~shiftClosedLoopErr(4) & shiftClosedLoopErr(3) ){
+    mirrorReg.io.addrB  := 13.U
+    mirrorReg.io.datawB := 1.U
+    mirrorReg.io.enwB   := true.B
+
+    ctrlUnicast := false.B
+  } .elsewhen( ~shiftClosedLoopErr(5) & shiftClosedLoopErr(4) ){
     interrupt     := true.B
   }
 
+
+
+
+  // when( lvdsMst.io.upstream_cdr_err ){
+  //   // statusCDRErr := true.B
+  //   mirrorReg.io.addrB  := 11.U
+  //   mirrorReg.io.datawB := 1.U
+  //   mirrorReg.io.enwB   := true.B   
+  //   interrupt     := true.B
+  // }
+
   when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
     // statusCRCErr := true.B
     mirrorReg.io.addrB  := 12.U