框架开始收尾,协调流水线
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@@ -10,25 +10,16 @@ class SubMsgTxInfo extends SubMsgHeader{
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class SlaveSendGenIO extends Bundle{
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val dataPing = Flipped( Decoupled(UInt(8.W)) )
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val dataPong = Flipped( Decoupled(UInt(8.W)) )
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val sram =
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val data = for( 0 until 2 ) yield { Flipped( Decoupled(UInt(8.W)) ) }
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// val stateNext = Output(UInt(4.W))
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// val stateCurr = Output(UInt(4.W))
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val frameReq = Flipped( Decoupled( new FrameHeader ) )
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val frameReq = Flipped(Decoupled( new FrameHeader ))
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val subMsgReq = Flipped(Decoupled( new SubMsgHeader ))
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val send = Decoupled(new AXIS_Bundle(8))
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}
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class SlaveSendGen extends Module{
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@@ -107,14 +98,14 @@ class SlaveSendGen extends Module{
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))
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val tdata_submsg_header = Mux1H(Seq(
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(lengthCnt === 0.U) -> subMsgInfoSel.subMsg_devIndex(13,6),
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(lengthCnt === 1.U) -> Cat( subMsgInfoSel.subMsg_devIndex(5,0), subMsgInfoSel.subMsg_style),
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(lengthCnt === 2.U) -> subMsgInfoSel.subMsg_address(15,8),
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(lengthCnt === 3.U) -> subMsgInfoSel.subMsg_address(7,0),
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(lengthCnt === 4.U) -> Cat(subMsgInfoSel.subMsg_operator, subMsgInfoSel.subMsg_length(11,8)),
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(lengthCnt === 5.U) -> subMsgInfoSel.subMsg_length(7,0),
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(lengthCnt === 6.U) -> subMsgInfoSel.subMsg_workCnt(15,8),
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(lengthCnt === 7.U) -> subMsgInfoSel.subMsg_workCnt(7,0),
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(lengthCnt === 0.U) -> subMsgInfoSel.devIndex(13,6),
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(lengthCnt === 1.U) -> Cat( subMsgInfoSel.devIndex(5,0), subMsgInfoSel.style),
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(lengthCnt === 2.U) -> subMsgInfoSel.address(15,8),
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(lengthCnt === 3.U) -> subMsgInfoSel.address(7,0),
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(lengthCnt === 4.U) -> Cat(subMsgInfoSel.operator, subMsgInfoSel.length(11,8)),
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(lengthCnt === 5.U) -> subMsgInfoSel.length(7,0),
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(lengthCnt === 6.U) -> subMsgInfoSel.workCnt(15,8),
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(lengthCnt === 7.U) -> subMsgInfoSel.workCnt(7,0),
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))
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val tdata_submsg_data = Mux1H(Seq(
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