137 lines
3.9 KiB
Scala
137 lines
3.9 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class SubMsgTxInfo extends SubMsgHeader{
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val source = UInt(2.W)
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}
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class SlaveSendGenIO extends Bundle{
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val data = for( 0 until 2 ) yield { Flipped( Decoupled(UInt(8.W)) ) }
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// val stateNext = Output(UInt(4.W))
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// val stateCurr = Output(UInt(4.W))
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val frameReq = Flipped(Decoupled( new FrameHeader ))
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val subMsgReq = Flipped(Decoupled( new SubMsgHeader ))
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val send = Decoupled(new AXIS_Bundle(8))
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}
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class SlaveSendGen extends Module{
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val io: SlaveSendGenIO = IO(new SlaveSendGenIO)
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val frameInfo = Reg(new FrameHeader)
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val subMsgInfoPing = Reg(new SubMsgHeader)
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val subMsgInfoPong = Reg(new SubMsgHeader)
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val isPingFill = RegInit(false.B)
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val isPingEmit = RegInit(false.B)
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when( io.frameReq.fire ){
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frameInfo := io.frameReq.bits
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}
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when( io.subMsgReq.fire ){
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when( isPingFill ){
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subMsgInfoPing := io.subMsgReq.bits
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} .otherwise{
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subMsgInfoPong := io.subMsgReq.bits
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}
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}
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val lengthCnt = Reg(UInt(12.W))
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val subMsgInfoSel = Mux( isPingEmit, subMsgInfoPing, subMsgInfoPong )
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val STATE_IDLE = 0.U //空闲
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val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型
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val STATE_SUBMSG_HEADER = 2.U
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val STATE_SUBMSG_DATA = 3.U
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val STATE_CRC = 4.U //CRC校验
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val STATE_ERROR = 5.U
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val STATE_WAIT = 6.U
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val stateNext = Wire(UInt(4.W))
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val stateCurr = RegNext(stateNext, STATE_IDLE(4.W))
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stateNext := Mux1H(Seq(
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(stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
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(stateCurr === STATE_FRAME_HEADER) -> Mux( lengthCnt === (2-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER),
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(stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (64-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER),
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(stateCurr === STATE_SUBMSG_DATA) ->
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Mux( lengthCnt === subMsgInfoSel.subMsg_length-1.U, //已经发送完成该子报文
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Mux( frameLenCnt === frameInfo.lengthCnt, STATE_CRC, //主报文长度达到， 进CRC
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Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ) ), //主报文长度未到，进下一个子报文
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STATE_SUBMSG_DATA
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),
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(stateCurr === STATE_CRC) -> Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC),
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(stateCurr === STATE_ERROR) ->
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(stateCurr === STATE_WAIT) ->
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))
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io.send.valid :=
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(stateCurr === STATE_FRAME_HEADER) |
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(stateCurr === STATE_SUBMSG_HEADER) |
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(stateCurr === STATE_SUBMSG_DATA) |
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(stateCurr === STATE_CRC)
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val tdata_frame_header = Mux1H(Seq(
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(lengthCnt === 0.U) -> frameLenAim(11,4),
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(lengthCnt === 1.U) -> Cat( frameLenAim(3,0), 0.U(2.W), frameStyle),
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))
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val tdata_submsg_header = Mux1H(Seq(
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(lengthCnt === 0.U) -> subMsgInfoSel.devIndex(13,6),
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(lengthCnt === 1.U) -> Cat( subMsgInfoSel.devIndex(5,0), subMsgInfoSel.style),
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(lengthCnt === 2.U) -> subMsgInfoSel.address(15,8),
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(lengthCnt === 3.U) -> subMsgInfoSel.address(7,0),
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(lengthCnt === 4.U) -> Cat(subMsgInfoSel.operator, subMsgInfoSel.length(11,8)),
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(lengthCnt === 5.U) -> subMsgInfoSel.length(7,0),
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(lengthCnt === 6.U) -> subMsgInfoSel.workCnt(15,8),
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(lengthCnt === 7.U) -> subMsgInfoSel.workCnt(7,0),
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))
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val tdata_submsg_data = Mux1H(Seq(
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(subMsgInfoSel.source === 0.U) -> dataPing.bits
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(subMsgInfoSel.source === 1.U) -> dataPong.bits
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(subMsgInfoSel.source === 2.U) -> sram.rdata
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))
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dataPing.ready :=
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dataPong.ready :=
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sram.enr :=
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val tdata_crc = Mux1H(Seq(
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))
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io.send.bits.tdata := Mux1H(Seq(
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(stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header,
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(stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
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(stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data,
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(stateCurr === STATE_CRC) -> tdata_crc,
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))
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io.send.bits.tuser :=
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io.send.bits.tlast :=
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} |