package BACK

import chisel3._
import chisel3.util._


class SubMsgTxInfo extends SubMsgHeader{
  val source = UInt(2.W)
}


class SlaveSendGenIO extends Bundle{
  val data = for( 0 until 2 ) yield { Flipped( Decoupled(UInt(8.W)) ) }

  // val stateNext = Output(UInt(4.W))
  // val stateCurr = Output(UInt(4.W))

  val frameReq  = Flipped(Decoupled( new FrameHeader ))
  val subMsgReq = Flipped(Decoupled( new SubMsgHeader ))

  val send = Decoupled(new AXIS_Bundle(8))

}

class SlaveSendGen extends Module{
  val io: SlaveSendGenIO = IO(new SlaveSendGenIO)


  val frameInfo = Reg(new FrameHeader)

  val subMsgInfoPing = Reg(new SubMsgHeader)
  val subMsgInfoPong = Reg(new SubMsgHeader)
  val isPingFill = RegInit(false.B)
  val isPingEmit = RegInit(false.B)


  when( io.frameReq.fire ){
    frameInfo := io.frameReq.bits
  }

  when( io.subMsgReq.fire ){
    when( isPingFill ){
      subMsgInfoPing := io.subMsgReq.bits
    } .otherwise{
      subMsgInfoPong := io.subMsgReq.bits
    }
  }

  val lengthCnt = Reg(UInt(12.W))




  val subMsgInfoSel = Mux( isPingEmit, subMsgInfoPing, subMsgInfoPong )





  val STATE_IDLE            = 0.U //空闲
  val STATE_FRAME_HEADER          = 1.U //长度/ /保留2bits //包类型
  val STATE_SUBMSG_HEADER = 2.U
  val STATE_SUBMSG_DATA   = 3.U
  val STATE_CRC             = 4.U //CRC校验
  val STATE_ERROR           = 5.U
  val STATE_WAIT            = 6.U


  val stateNext = Wire(UInt(4.W))
  val stateCurr = RegNext(stateNext, STATE_IDLE(4.W))

  stateNext := Mux1H(Seq(
    (stateCurr === STATE_IDLE)          -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
    (stateCurr === STATE_FRAME_HEADER)  -> Mux( lengthCnt === (2-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER),
    (stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (64-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER),
    (stateCurr === STATE_SUBMSG_DATA)   ->
      Mux( lengthCnt === subMsgInfoSel.subMsg_length-1.U,    //已经发送完成该子报文
        Mux( frameLenCnt === frameInfo.lengthCnt, STATE_CRC, //主报文长度达到， 进CRC
          Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ) ), //主报文长度未到，进下一个子报文
        STATE_SUBMSG_DATA
      ),
    (stateCurr === STATE_CRC)           -> Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC),
    (stateCurr === STATE_ERROR)         ->
    (stateCurr === STATE_WAIT)          ->
  ))


  io.send.valid := 
    (stateCurr === STATE_FRAME_HEADER) |
    (stateCurr === STATE_SUBMSG_HEADER) |
    (stateCurr === STATE_SUBMSG_DATA) |
    (stateCurr === STATE_CRC)


  val tdata_frame_header = Mux1H(Seq(
    (lengthCnt === 0.U) -> frameLenAim(11,4),
    (lengthCnt === 1.U) -> Cat( frameLenAim(3,0), 0.U(2.W), frameStyle),
  ))

  val tdata_submsg_header = Mux1H(Seq(
    (lengthCnt === 0.U) -> subMsgInfoSel.devIndex(13,6),
    (lengthCnt === 1.U) -> Cat( subMsgInfoSel.devIndex(5,0), subMsgInfoSel.style),
    (lengthCnt === 2.U) -> subMsgInfoSel.address(15,8),
    (lengthCnt === 3.U) -> subMsgInfoSel.address(7,0),
    (lengthCnt === 4.U) -> Cat(subMsgInfoSel.operator, subMsgInfoSel.length(11,8)),
    (lengthCnt === 5.U) -> subMsgInfoSel.length(7,0),
    (lengthCnt === 6.U) -> subMsgInfoSel.workCnt(15,8),
    (lengthCnt === 7.U) -> subMsgInfoSel.workCnt(7,0),
  ))

  val tdata_submsg_data = Mux1H(Seq(
    (subMsgInfoSel.source === 0.U) -> dataPing.bits
    (subMsgInfoSel.source === 1.U) -> dataPong.bits
    (subMsgInfoSel.source === 2.U) -> sram.rdata
  ))

  dataPing.ready := 
  dataPong.ready := 
  sram.enr := 

  val tdata_crc = Mux1H(Seq(

  ))

  io.send.bits.tdata := Mux1H(Seq(
    (stateCurr === STATE_FRAME_HEADER)  -> tdata_frame_header,
    (stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
    (stateCurr === STATE_SUBMSG_DATA)   -> tdata_submsg_data,
    (stateCurr === STATE_CRC)           -> tdata_crc,
  ))

  io.send.bits.tuser := 
  io.send.bits.tlast := 



}