From d7b04710ae2c22b14241bf33510904137b757eaa Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 8 Apr 2025 17:29:45 +0800 Subject: [PATCH] =?UTF-8?q?=E6=A1=86=E6=9E=B6=E5=BC=80=E5=A7=8B=E6=94=B6?= =?UTF-8?q?=E5=B0=BE=EF=BC=8C=E5=8D=8F=E8=B0=83=E6=B5=81=E6=B0=B4=E7=BA=BF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 259 +++++++++++++----- .../scala/backBoard/shin/SlaveRecParser.scala | 57 ++-- .../scala/backBoard/shin/SlaveSendGen.scala | 29 +- 3 files changed, 226 insertions(+), 119 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 1a1d78c..813f716 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -10,12 +10,12 @@ class FrameHeader extends Bundle{ } class SubMsgHeader extends Bundle{ - val subMsg_devIndex = UInt(14.W) // 子报文中设备索引 - val subMsg_style = UInt(2.W) // 子报文类型 - val subMsg_address = UInt(16.W) //子报文地址 - val subMsg_operator = UInt(4.W) //子报文命令类型 - val subMsg_length = UInt(12.W) //子报文负载长度 - val subMsg_workCnt = UInt(16.W) //子报文工作计数 + val devIndex = UInt(14.W) // 子报文中设备索引 + val style = UInt(2.W) // 子报文类型 + val address = UInt(16.W) //子报文地址 + val operator = UInt(4.W) //子报文命令类型 + val length = UInt(12.W) //子报文负载长度 + val workCnt = UInt(16.W) //子报文工作计数 } @@ -56,8 +56,7 @@ abstract class SlaveParserBase extends Module{ val upSendGen = Module(new SlaveSendGen) - val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } - val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } + val downSinkSel = Reg(Bool()) @@ -76,6 +75,9 @@ abstract class SlaveParserBase extends Module{ val isUpSendPend = RegInit(false.B) + + //处理主报文 + //同时到来怎么办 when( downRecParser.io.frameReq.fire ){ when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包 @@ -118,13 +120,14 @@ abstract class SlaveParserBase extends Module{ } upSendGen.io.frameReq.valid := - isUpSendPend | isUpSendProbe //上行转发 | 上行探针 + isUpSendPend | isUpSendProbe | //上行转发 | 上行探针 | 下行回环 assert( OneHot(isUpSendPend, isUpSendProbe) ) upSendGen.io.frameReq.bits := Mux1H(Seq( isUpSendPend -> upFrameInfo, //上行转发 isUpSendProbe -> probeFrame, //上行探针 + , //下行回环 )) @@ -139,91 +142,217 @@ abstract class SlaveParserBase extends Module{ + //子报文 + val isDownSubMsgValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val isUpSubMsgValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } + //接收子报文 - upSendFifo.io.enq.bits := Mux1H(Seq( - ( downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) -> downRecParser.io.data.bits //嗅探包 bypass到上行 + val downSubMsgInfo = for( i <- 0 until 2 ) yield { Reg(new SubMsgHeader) } + val upSubMsgInfo = for( i <- 0 until 2 ) yield { Reg(new SubMsgHeader) } + + + val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } + val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } + + val isDownRecPing: Bool + val isUpRecPing: Bool + + + + //下行接收 + when( downRecParser.io.subMsgReq.fire ){ + when( isDownRecPing ){ + isDownSubMsgValid(0) := true.B + + downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex + downSubMsgInfo(0).style := downRecParser.io.subMsgReq.bits.style + downSubMsgInfo(0).address := downRecParser.io.subMsgReq.bits.address + downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator + downSubMsgInfo(0).length := downRecParser.io.subMsgReq.bits.length + downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + downSubMsgInfo(0).source := 0.U + + //override 自身包 + when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ + when( downRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram + downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + } .elsewhen( downRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo + } .elsewhen( downRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo + downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + } + } + } .otherwise{ + isDownSubMsgValid(1) := true.B + + downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex + downSubMsgInfo(1).style := downRecParser.io.subMsgReq.bits.style + downSubMsgInfo(1).address := downRecParser.io.subMsgReq.bits.address + downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator + downSubMsgInfo(1).length := downRecParser.io.subMsgReq.bits.length + downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + downSubMsgInfo(1).source := 1.U + + //override 自身包 + when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ + when( downRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram + downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + } .elsewhen( downRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo + } .elsewhen( downRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo + downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + } + } + } + } + + + + + when( isDownRecPing ){ + downRecFifo(0).io.enq.valid := downRecParser.io.data.valid + downRecFifo(0).io.enq.bits := downRecParser.io.data.bits + downRecParser.io.data.ready := downRecFifo(0).io.enq.ready + } .otherwise{ + downRecFifo(1).io.enq.valid := downRecParser.io.data.valid + downRecFifo(1).io.enq.bits := downRecParser.io.data.bits + downRecParser.io.data.ready := downRecFifo(1).io.enq.ready + } + + //写入sram + sram.io.enw := + ( isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) | + (~isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U)) - )) - upSendFifo.io.enq.valid := - ((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & downRecParser.io.data.valid) | - - downRecParser.io.data.ready := - ((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & upSendFifo.io.enq.ready ) | - - - downSendFifo.io.enq.bits := Mux1H(Seq( - ( downRecParser.io.frameStyle === FRAME_STYLE_COMMON & downRecParser.io.stateCurr > STATE_HEADER ) -> - )) - - - - val isDownIdle - val isDownBypassToDown - val isDownWriteToSRAM - val isDownReadFromSRAM - val isDownLoopBack - - val isUpIdle - val isUpBypassToUp - val isUpWriteToSRAM - val isUpReadFromSRAM - val isUpBlackHole + sram.io.addrw := + sram.io.dataw := downRecParser.io.data.bits + //上行接收 + when( upRecParser.io.subMsgReq.fire ){ + when( isUpRecFifoPing ){ + isUpSubMsgValid(0) := true.B - // val downOutFifo = Module(new Queue(UInt(8.W), 8)) - val upInFifo = Module(new Queue(UInt(8.W), 8)) - // val upOutFifo = Module(new Queue(UInt(8.W), 8)) + upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex + upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style + upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address + upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator + upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length + upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + upSubMsgInfo(0).source := 0.U + + //override 自身包 + when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ + when( upRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram + } .elsewhen( upRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo + upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U + } .elsewhen( upRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo + upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U + } + } + } .otherwise{ + isUpSubMsgValid(1) := true.B + + upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex + upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style + upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address + upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator + upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length + upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + upSubMsgInfo(1).source := 1.U + + //override 自身包 + when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ + when( upRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram + } .elsewhen( upRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo + upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U + } .elsewhen( upRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo + upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U + } + } + } + } + + when( isUpRecFifoPing ){ + upRecFifo(0).io.enq.valid := upRecParser.io.data.valid + upRecFifo(0).io.enq.bits := + Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U), + sram.io.datar, upRecParser.io.data.bits) - downInFifo.io.enq <> io.downIn + upRecParser.io.data.ready := upRecFifo(0).io.enq.ready + } .otherwise{ + upRecFifo(1).io.enq.valid := upRecParser.io.data.valid + upRecFifo(1).io.enq.bits := Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U), + sram.io.datar, upRecParser.io.data.bits) + upRecParser.io.data.ready := upRecFifo(1).io.enq.ready + } - io.downOut.valid := - ( === FRAME_STYLE_COMMON ) & - - io.upOut.valid := - ( === FRAME_STYLE_PROBE) & | - - io.upOut.bits := - Mux1H(Seq( - ( === FRAME_STYLE_PROBE) -> downInFifo.io.deq.bits, //嗅探包情形 - -> upInFifo.io.deq.bits, //上行 - -> //上行修正数据 - )) - - io.downOut.bits := - Mux1H(Seq( - -> //自主发送嗅探包 - ( ) -> downInFifo.io.deq.bits, //下行 - ( ) -> //下行修正数据 - )) - - - - - downInFifo.io.deq.ready := - upInFifo.io.deq.ready := + //读出SRAM + sram.io.enr := + ( isUpRecFifoPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 1.U | upSubMsgInfo(0).operator === 3.U)) | + (~isUpRecFifoPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 1.U | upSubMsgInfo(1).operator === 3.U)) + sram.io.addrr := + //子报文下行发送 + val isDownSendPing: Bool + val isUpSendPing: Bool + val isLastDevice: Bool + + downSendGen.io.subMsgReq.valid := + ( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1)) + + downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) ) + + when( downSendGen.io.subMsgReq.fire ){ //ready + isDownSendPing := ~isDownSendPing + when( isDownSendPing ){ + isDownSubMsgValid(0) := false.B + } .otherwise{ + isDownSubMsgValid(1) := false.B + } + } + downRecFifo(0).io.deq <> downSendGen.io.data(0) + downRecFifo(1).io.deq <> downSendGen.io.data(1) + + //子报文上行发送 + + upSendGen.io.subMsgReq.valid := + ( isUpSendPing & isUpSubMsgValid(0) ) | (~isUpSendPing & isUpSubMsgValid(1)) + + upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) ) + + when( upSendGen.io.subMsgReq.fire ){ //ready + isUpSendPing := ~isUpSendPing + when( isUpSendPing ){ + isUpSubMsgValid(0) := false.B + } .otherwise{ + isUpSubMsgValid(1) := false.B + } + } + upRecFifo(0).io.deq <> upSendGen.io.data(0) + upRecFifo(1).io.deq <> upSendGen.io.data(1) + when(isLastDevice & downRecParser.io.stateCurr > ){ + downSendGen.io.send <> upRecParser.io.rec + } diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index 7251c2a..0329f55 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -12,21 +12,11 @@ class SlaveRecParserIO extends Module{ val stateNext = Output(UInt(4.W)) val stateCurr = Output(UInt(4.W)) - val frameReq = Valid( new Bundle{ - val frameLenAim = Output(UInt(12.W)) //帧长度目标 - val frameStyle = Output(UInt(2.W)) //包类型 - } ) - - val subMsgReq = Valid( new Bundle{ - val subMsg_devIndex = Output(UInt(14.W)) // 子报文中设备索引 - val subMsg_style = Output(UInt(2.W)) // 子报文类型 - val subMsg_address = Output(UInt(16.W)) //子报文地址 - val subMsg_operator = Output(UInt(4.W)) //子报文命令类型 - val subMsg_length = Output(UInt(12.W)) //子报文负载长度 - val subMsg_workCnt = Output(UInt(16.W)) //子报文工作计数 - ) - + val frameReq = Valid( new FrameHeader ) + val subMsgReq = Valid( new SubMsgHeader ) + val resp = Input(Bool()) + val isError = Output(Bool()) } @@ -35,8 +25,6 @@ class SlaveRecParser extends Module{ val io: SlaveRecParserIO = IO(new SlaveRecParserIO) - - val FRAME_STYLE_COMMON = 0.U val FRAME_STYLE_PROBE = 1.U @@ -59,18 +47,17 @@ class SlaveRecParser extends Module{ val lengthCnt = Reg(UInt(11.W)) //动态计数器 val frameLenCnt = Reg(UInt(12.W)) //帧长度计数 val isCrcPass: Bool - val isTxEnd: Bool val isShortRx: Bool //接收长度小于预期 val frameLenAim = Reg(UInt(12.W)); io.frameLenAim := frameLenAim //帧长度目标 val frameStyle = Reg(UInt(2.W)); io.frameStyle := frameStyle //包类型 - val subMsg_devIndex = Reg(UInt(14.W)); io.subMsg_devIndex := subMsg_devIndex // 子报文中设备索引 - val subMsg_style = Reg(UInt(2.W)); io.subMsg_style := subMsg_style // 子报文类型 - val subMsg_address = Reg(UInt(16.W)); io.subMsg_address := subMsg_address //子报文地址 - val subMsg_operator = Reg(UInt(4.W)); io.subMsg_operator := subMsg_operator //子报文命令类型 - val subMsg_length = Reg(UInt(12.W)); io.subMsg_length := subMsg_length //子报文负载长度 - val subMsg_workCnt = Reg(UInt(16.W)); io.subMsg_workCnt := subMsg_workCnt //子报文工作计数 + val devIndex = Reg(UInt(14.W)); io.subMsgReq.devIndex := devIndex // 子报文中设备索引 + val style = Reg(UInt(2.W)); io.subMsgReq.style := style // 子报文类型 + val address = Reg(UInt(16.W)); io.subMsgReq.address := address //子报文地址 + val operator = Reg(UInt(4.W)); io.subMsgReq.operator := operator //子报文命令类型 + val length = Reg(UInt(12.W)); io.subMsgReq.length := length //子报文负载长度 + val workCnt = Reg(UInt(16.W)); io.subMsgReq.workCnt := workCnt //子报文工作计数 when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){ @@ -81,29 +68,29 @@ class SlaveRecParser extends Module{ } when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){ - subMsg_devIndex := io.rec.bits.tdata << 6 + devIndex := io.rec.bits.tdata << 6 } .elsewhen( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){ - subMsg_devIndex := subMsg_devIndex | io.rec.bits.tdata(7,2) - subMsg_style := io.rec.bits.tdata(1,0) + devIndex := devIndex | io.rec.bits.tdata(7,2) + style := io.rec.bits.tdata(1,0) } when( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){ - subMsg_address := io.rec.bits.tdata << 8 + address := io.rec.bits.tdata << 8 } .elsewhen( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){ - subMsg_address := subMsg_address | io.rec.bits.tdata + address := address | io.rec.bits.tdata } when( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){ - subMsg_operator := io.rec.bits.tdata(7,4) - subMsg_length := io.rec.bits.tdata(3,0) << 8 + operator := io.rec.bits.tdata(7,4) + length := io.rec.bits.tdata(3,0) << 8 } .elsewhen( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){ - subMsg_length := subMsg_length | io.rec.bits.tdata(7,0) + length := length | io.rec.bits.tdata(7,0) } when( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){ - subMsg_workCnt := io.rec.bits.tdata(7,0) << 8 + workCnt := io.rec.bits.tdata(7,0) << 8 } .elsewhen( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){ - subMsg_workCnt := subMsg_workCnt | io.rec.bits.tdata(7,0) + workCnt := workCnt | io.rec.bits.tdata(7,0) } @@ -139,8 +126,8 @@ class SlaveRecParser extends Module{ ( stateCurr === STATE_CRC ) -> Mux( isShortRx, STATE_ERROR, Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), STATE_CRC ) ), - ( stateCurr === STATE_ERROR ) -> Mux( isTxEnd, STATE_IDLE, STATE_ERROR ), - ( stateCurr === STATE_WAIT ) -> + ( stateCurr === STATE_ERROR ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR ), + ( stateCurr === STATE_WAIT ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR ) )) diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index 5ca046e..560da95 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -10,25 +10,16 @@ class SubMsgTxInfo extends SubMsgHeader{ class SlaveSendGenIO extends Bundle{ - - - val dataPing = Flipped( Decoupled(UInt(8.W)) ) - val dataPong = Flipped( Decoupled(UInt(8.W)) ) - val sram = + val data = for( 0 until 2 ) yield { Flipped( Decoupled(UInt(8.W)) ) } // val stateNext = Output(UInt(4.W)) // val stateCurr = Output(UInt(4.W)) - - val frameReq = Flipped( Decoupled( new FrameHeader ) ) - + val frameReq = Flipped(Decoupled( new FrameHeader )) val subMsgReq = Flipped(Decoupled( new SubMsgHeader )) - - val send = Decoupled(new AXIS_Bundle(8)) - } class SlaveSendGen extends Module{ @@ -107,14 +98,14 @@ class SlaveSendGen extends Module{ )) val tdata_submsg_header = Mux1H(Seq( - (lengthCnt === 0.U) -> subMsgInfoSel.subMsg_devIndex(13,6), - (lengthCnt === 1.U) -> Cat( subMsgInfoSel.subMsg_devIndex(5,0), subMsgInfoSel.subMsg_style), - (lengthCnt === 2.U) -> subMsgInfoSel.subMsg_address(15,8), - (lengthCnt === 3.U) -> subMsgInfoSel.subMsg_address(7,0), - (lengthCnt === 4.U) -> Cat(subMsgInfoSel.subMsg_operator, subMsgInfoSel.subMsg_length(11,8)), - (lengthCnt === 5.U) -> subMsgInfoSel.subMsg_length(7,0), - (lengthCnt === 6.U) -> subMsgInfoSel.subMsg_workCnt(15,8), - (lengthCnt === 7.U) -> subMsgInfoSel.subMsg_workCnt(7,0), + (lengthCnt === 0.U) -> subMsgInfoSel.devIndex(13,6), + (lengthCnt === 1.U) -> Cat( subMsgInfoSel.devIndex(5,0), subMsgInfoSel.style), + (lengthCnt === 2.U) -> subMsgInfoSel.address(15,8), + (lengthCnt === 3.U) -> subMsgInfoSel.address(7,0), + (lengthCnt === 4.U) -> Cat(subMsgInfoSel.operator, subMsgInfoSel.length(11,8)), + (lengthCnt === 5.U) -> subMsgInfoSel.length(7,0), + (lengthCnt === 6.U) -> subMsgInfoSel.workCnt(15,8), + (lengthCnt === 7.U) -> subMsgInfoSel.workCnt(7,0), )) val tdata_submsg_data = Mux1H(Seq(