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异步QSPI的方向控制挪到下降沿，时序逻辑控制

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RuigeLee
2026-02-14 09:55:24 +08:00
parent 44b7aa2a5d
commit d50076f932
1 changed files with 6 additions and 1 deletions
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7
src/main/scala/backBoard/shin/NSpiInterface.scala
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@@ -18,6 +18,8 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
val bitSel = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) }
val byteSel = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(12.W))}
val exRego = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
val isDirIn = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(true.B)}
qspi.isDirIn := isDirIn
val exRegi = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
@@ -69,7 +71,10 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
qspi.miso := exRego(7, 4)
qspi.isDirIn := isSpiWrite | (byteSel <= 3.U)
when( byteSel === 4.U & bitSel === 0.U ){
isDirIn := isSpiWrite
}
when( (if( OPER114 ) { byteSel <= 3.U } else {false.B}) ){ //单线操作
bitSel := bitSel + 1.U