From d50076f932e33be021963a0ab4aed917b110bf37 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Sat, 14 Feb 2026 09:55:24 +0800 Subject: [PATCH] =?UTF-8?q?=E5=BC=82=E6=AD=A5QSPI=E7=9A=84=E6=96=B9?= =?UTF-8?q?=E5=90=91=E6=8E=A7=E5=88=B6=E6=8C=AA=E5=88=B0=E4=B8=8B=E9=99=8D?= =?UTF-8?q?=E6=B2=BF=EF=BC=8C=E6=97=B6=E5=BA=8F=E9=80=BB=E8=BE=91=E6=8E=A7?= =?UTF-8?q?=E5=88=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/NSpiInterface.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala index 173bbf2..a4d64f0 100644 --- a/src/main/scala/backBoard/shin/NSpiInterface.scala +++ b/src/main/scala/backBoard/shin/NSpiInterface.scala @@ -18,6 +18,8 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{ val bitSel = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) } val byteSel = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(12.W))} val exRego = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))} + val isDirIn = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(true.B)} + qspi.isDirIn := isDirIn val exRegi = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))} val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } @@ -69,8 +71,11 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase => qspi.miso := exRego(7, 4) - qspi.isDirIn := isSpiWrite | (byteSel <= 3.U) + when( byteSel === 4.U & bitSel === 0.U ){ + isDirIn := isSpiWrite + } + when( (if( OPER114 ) { byteSel <= 3.U } else {false.B}) ){ //单线操作 bitSel := bitSel + 1.U } .otherwise{ //4线操作