diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala
index 173bbf2..a4d64f0 100644
--- a/src/main/scala/backBoard/shin/NSpiInterface.scala
+++ b/src/main/scala/backBoard/shin/NSpiInterface.scala
@@ -18,6 +18,8 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
   val bitSel  = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) }
   val byteSel = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(12.W))}
   val exRego  = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
+  val isDirIn = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(true.B)}
+  qspi.isDirIn := isDirIn
   val exRegi  = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
   val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
   val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
@@ -69,8 +71,11 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
 
 
   qspi.miso := exRego(7, 4)
-  qspi.isDirIn := isSpiWrite | (byteSel <= 3.U)
 
+  when( byteSel === 4.U & bitSel === 0.U ){
+    isDirIn := isSpiWrite
+  }
+  
   when( (if( OPER114 ) { byteSel <= 3.U } else {false.B}) ){ //单线操作
     bitSel := bitSel + 1.U
   } .otherwise{ //4线操作