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物理层和链路层的包头一起合并处理

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RuigeLee
2024-10-17 11:54:02 +08:00
parent ab0fab00fa
commit d449980b5b
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -64,7 +64,7 @@ trait CDRInOverSample{ this: CDRInBase =>
trait CDRInAxis{ this: CDRInBase => trait CDRInAxis{ this: CDRInBase =>
def HeaderByte: Int = 4 def HeaderByte: Int = 8
val ETH_PRE = "h55".U val ETH_PRE = "h55".U
val ETH_SFD = "hD5".U val ETH_SFD = "hD5".U
@@ -138,7 +138,7 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B) val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ) val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 7.U ) val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 7.U )
val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 7.U ) val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 7.U )
@@ -150,7 +150,7 @@ trait CDRInAxis{ this: CDRInBase =>
when( io.axis.fire ){ when( io.axis.fire ){
axis_valid := false.B axis_valid := false.B
} .elsewhen( bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){ } .elsewhen( bitCnt === 7.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
axis_valid := true.B axis_valid := true.B
} }