From d449980b5b4c866dce63408457f786375c92f788 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 17 Oct 2024 11:54:02 +0800 Subject: [PATCH] =?UTF-8?q?=E7=89=A9=E7=90=86=E5=B1=82=E5=92=8C=E9=93=BE?= =?UTF-8?q?=E8=B7=AF=E5=B1=82=E7=9A=84=E5=8C=85=E5=A4=B4=E4=B8=80=E8=B5=B7?= =?UTF-8?q?=E5=90=88=E5=B9=B6=E5=A4=84=E7=90=86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 373f7fe..2b49e71 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -64,7 +64,7 @@ trait CDRInOverSample{ this: CDRInBase => trait CDRInAxis{ this: CDRInBase => - def HeaderByte: Int = 4 + def HeaderByte: Int = 8 val ETH_PRE = "h55".U val ETH_SFD = "hD5".U @@ -138,7 +138,7 @@ trait CDRInAxis{ this: CDRInBase => val axis_valid = RegInit(false.B) - val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ) + val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ) val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 7.U ) val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 7.U ) @@ -150,7 +150,7 @@ trait CDRInAxis{ this: CDRInBase => when( io.axis.fire ){ axis_valid := false.B - } .elsewhen( bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){ + } .elsewhen( bitCnt === 7.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){ axis_valid := true.B }