diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 373f7fe..2b49e71 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -64,7 +64,7 @@ trait CDRInOverSample{ this: CDRInBase =>
 
 trait CDRInAxis{ this: CDRInBase =>
 
-  def HeaderByte: Int = 4
+  def HeaderByte: Int = 8
 
   val ETH_PRE = "h55".U
   val ETH_SFD = "hD5".U
@@ -138,7 +138,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
 
   val axis_valid = RegInit(false.B)
-  val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
+  val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
   val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )),  bitCnt === 7.U )
   val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U,                                                 bitCnt === 7.U )
 
@@ -150,7 +150,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
   when( io.axis.fire ){
     axis_valid := false.B
-  } .elsewhen( bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
+  } .elsewhen( bitCnt === 7.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
     axis_valid := true.B
   }