ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

spi初始值改为1

Browse Source
This commit is contained in:
Ruige Lee
2025-08-12 17:54:24 +08:00
parent 89071e4973
commit d045705950
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -614,7 +614,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U ) cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U ) cReg.spiSel := RegEnable( dataw(1,0), 1.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
cReg.pllCtrl := cReg.pllCtrl :=
Cat( Cat(