From d045705950a2d1d0d968dea351bddf8b8b176de6 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 12 Aug 2025 17:54:24 +0800 Subject: [PATCH] =?UTF-8?q?spi=E5=88=9D=E5=A7=8B=E5=80=BC=E6=94=B9?= =?UTF-8?q?=E4=B8=BA1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 5233306..b8b0791 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -614,7 +614,7 @@ trait InterfaceMCUop{ this: InterfaceBase => cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U ) - cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U ) + cReg.spiSel := RegEnable( dataw(1,0), 1.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U ) cReg.pllCtrl := Cat(