diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 5233306..b8b0791 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -614,7 +614,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
   
   cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
-  cReg.spiSel  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
+  cReg.spiSel  := RegEnable( dataw(1,0), 1.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
 
   cReg.pllCtrl := 
     Cat(